8561ad9296
Native register descriptions in LLDB specify lldb register numbers in value_regs and invalidate_regs lists. These register numbers may not match with Process gdb-remote register numbers which are generated by native process after counting all registers in its register sets. It was coincidentally not causing any problems as we never came across a native target with dynamically changing register sets and register numbers generated by counter matched with LLDB native register numbers. This came up while testing target AArch64 SVE which can choose register sets based on underlying hardware. This patch fixes this behavior and always tries to use remote register numbers while reading/writing registers over gdb-remote protocol. Reviewed By: labath Differential Revision: https://reviews.llvm.org/D77043
127 lines
5.7 KiB
Python
127 lines
5.7 KiB
Python
from __future__ import print_function
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import lldb
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from gdbclientutils import *
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# This test case checks for register number mismatch between lldb and gdb stub.
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# LLDB client assigns register numbers to target xml registers in increasing
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# order starting with regnum = 0, while gdb-remote may specify different regnum
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# which is stored as eRegisterKindProcessPlugin. Remote side will use its
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# register number in expedited register list, value_regs and invalidate_regnums.
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#
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# This test creates a ficticious target xml with non-sequential regnums to test
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# that correct registers are accessed in all of above mentioned cases.
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class TestRemoteRegNums(GDBRemoteTestBase):
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@skipIfXmlSupportMissing
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def test(self):
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class MyResponder(MockGDBServerResponder):
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def haltReason(self):
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return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;00:00bc010001000000;09:c04825ebfe7f0000;"
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def threadStopInfo(self, threadnum):
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return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;00:00bc010001000000;09:c04825ebfe7f0000;"
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def writeRegisters(self):
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return "E02"
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def readRegisters(self):
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return "E01"
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rax_regnum2_val = "7882773ce0ffffff"
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rbx_regnum4_val = "1122334455667788"
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def readRegister(self, regnum):
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# lldb will try sending "p0" to see if the p packet is supported,
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# give a bogus value; in theory lldb could use this value in the
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# register context and that would be valid behavior.
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# notably, don't give values for registers 1 & 3 -- lldb should
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# get those from the ? stop packet ("T11") and it is a pref regression
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# if lldb is asking for these register values.
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if regnum == 0:
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return "5555555555555555"
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if regnum == 2:
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return self.rax_regnum2_val
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if regnum == 4:
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return self.rbx_regnum4_val
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return "E03"
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def writeRegister(self, regnum, value_hex):
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if regnum == 2:
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self.rax_regnum2_val = value_hex
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if regnum == 4:
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self.rbx_regnum4_val = value_hex
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return "OK"
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return """<?xml version="1.0"?>
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<target version="1.0">
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<architecture>i386:x86-64</architecture>
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<feature name="org.gnu.gdb.i386.core">
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<reg name="rip" bitsize="64" regnum="0" type="code_ptr" group="general" altname="pc" generic="pc"/>
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<reg name="rax" bitsize="64" regnum="2" type="code_ptr" group="general"/>
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<reg name="rbx" bitsize="64" regnum="4" type="code_ptr" group="general"/>
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<reg name="eax" bitsize="32" regnum="5" value_regnums="2" invalidate_regnums="2" type="code_ptr" group="general"/>
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<reg name="ebx" bitsize="32" regnum="7" value_regnums="4" invalidate_regnums="4" type="code_ptr" group="general"/>
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<reg name="rsi" bitsize="64" regnum="9" type="code_ptr" group="general"/>
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</feature>
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</target>""", False
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else:
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return None, False
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self.server.responder = MyResponder()
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target = self.dbg.CreateTarget('')
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if self.TraceOn():
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self.runCmd("log enable gdb-remote packets")
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self.addTearDownHook(
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lambda: self.runCmd("log disable gdb-remote packets"))
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process = self.connect(target)
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thread = process.GetThreadAtIndex(0)
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frame = thread.GetFrameAtIndex(0)
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rax = frame.FindRegister("rax").GetValueAsUnsigned()
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eax = frame.FindRegister("eax").GetValueAsUnsigned()
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rbx = frame.FindRegister("rbx").GetValueAsUnsigned()
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ebx = frame.FindRegister("ebx").GetValueAsUnsigned()
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rsi = frame.FindRegister("rsi").GetValueAsUnsigned()
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pc = frame.GetPC()
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rip = frame.FindRegister("rip").GetValueAsUnsigned()
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if self.TraceOn():
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print("Register values: rax == 0x%x, rbx == 0x%x, rsi == 0x%x, pc == 0x%x, rip == 0x%x" % (
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rax, rbx, rsi, pc, rip))
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self.assertEqual(rax, 0xffffffe03c778278)
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self.assertEqual(rbx, 0x8877665544332211)
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self.assertEqual(eax, 0x3c778278)
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self.assertEqual(ebx, 0x44332211)
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self.assertEqual(rsi, 0x00007ffeeb2548c0)
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self.assertEqual(pc, 0x10001bc00)
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self.assertEqual(rip, 0x10001bc00)
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frame.FindRegister("eax").SetValueFromCString("1")
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frame.FindRegister("ebx").SetValueFromCString("0")
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eax = frame.FindRegister("eax").GetValueAsUnsigned()
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ebx = frame.FindRegister("ebx").GetValueAsUnsigned()
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rax = frame.FindRegister("rax").GetValueAsUnsigned()
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rbx = frame.FindRegister("rbx").GetValueAsUnsigned()
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if self.TraceOn():
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print("Register values: rax == 0x%x, rbx == 0x%x, rsi == 0x%x, pc == 0x%x, rip == 0x%x" % (
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rax, rbx, rsi, pc, rip))
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self.assertEqual(rax, 0xffffffe000000001)
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self.assertEqual(rbx, 0x8877665500000000)
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self.assertEqual(eax, 0x00000001)
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self.assertEqual(ebx, 0x00000000)
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self.assertEqual(rsi, 0x00007ffeeb2548c0)
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self.assertEqual(pc, 0x10001bc00)
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self.assertEqual(rip, 0x10001bc00)
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