63b0f8c788
Currently the ItaniumRecordLayoutBuilder when laying out base classes has the virtual and non-virtual bases mixed up when pulling the base class layouts from the external source. This came up in an LLDB bug where on arm64 because of differences in how it deals with tail padding would layout the bases differently without the correct layout from the external source (LLDB). This would result in some fields being off by 4 bytes. Differential Revision: https://reviews.llvm.org/D83008
17 lines
473 B
Python
17 lines
473 B
Python
import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class TestCase(TestBase):
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mydir = TestBase.compute_mydir(__file__)
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@no_debug_info_test
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def test(self):
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self.build()
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self.dbg.CreateTarget(self.getBuildArtifact("a.out"))
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# The offset of f2 should be 8 because of `alignas(8)`.
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self.expect_expr("(intptr_t)&d3g.f2 - (intptr_t)&d3g", result_value="8")
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