89b57061f7
This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454
137 lines
4.1 KiB
C++
137 lines
4.1 KiB
C++
//===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AVR specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRTargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "AVR.h"
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#include "AVRTargetObjectFile.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "TargetInfo/AVRTargetInfo.h"
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namespace llvm {
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static const char *AVRDataLayout =
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"e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
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/// Processes a CPU name.
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static StringRef getCPU(StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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return "avr2";
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}
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return CPU;
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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return RM.getValueOr(Reloc::Static);
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}
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AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {
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this->TLOF = std::make_unique<AVRTargetObjectFile>();
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initAsmInfo();
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}
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namespace {
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/// AVR Code Generator Pass Configuration Options.
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class AVRPassConfig : public TargetPassConfig {
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public:
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AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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AVRTargetMachine &getAVRTargetMachine() const {
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return getTM<AVRTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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} // namespace
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TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AVRPassConfig(*this, PM);
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}
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void AVRPassConfig::addIRPasses() {
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// Expand instructions like
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// %result = shl i32 %n, %amount
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// to a loop so that library calls are avoided.
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addPass(createAVRShiftExpandPass());
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TargetPassConfig::addIRPasses();
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
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// Register the target.
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RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
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auto &PR = *PassRegistry::getPassRegistry();
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initializeAVRExpandPseudoPass(PR);
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initializeAVRRelaxMemPass(PR);
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initializeAVRShiftExpandPass(PR);
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
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return &SubTarget;
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
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return &SubTarget;
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool AVRPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
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// Create the frame analyzer pass used by the PEI pass.
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addPass(createAVRFrameAnalyzerPass());
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return false;
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}
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void AVRPassConfig::addPreRegAlloc() {
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// Create the dynalloc SP save/restore pass to handle variable sized allocas.
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addPass(createAVRDynAllocaSRPass());
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}
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void AVRPassConfig::addPreSched2() {
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addPass(createAVRRelaxMemPass());
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addPass(createAVRExpandPseudoPass());
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}
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void AVRPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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addPass(&BranchRelaxationPassID);
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}
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} // end of namespace llvm
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