9647a6f719
This to protect against non-sensical instruction sequences being assembled, which would either cause asserts/crashes further down, or a Wasm module being output that doesn't validate. Unlike a validator, this type checker is able to give type-errors as part of the parsing process, which makes the assembler much friendlier to be used by humans writing manual input. Because the MC system is single pass (instructions aren't even stored in MC format, they are directly output) the type checker has to be single pass as well, which means that from now on .globaltype and .functype decls must come before their use. An extra pass is added to Codegen to collect information for this purpose, since AsmPrinter is normally single pass / streaming as well, and would otherwise generate this information on the fly. A `-no-type-check` flag was added to llvm-mc (and any other tools that take asm input) that surpresses type errors, as a quick escape hatch for tests that were not intended to be type correct. This is a first version of the type checker that ignores control flow, i.e. it checks that types are correct along the linear path, but not the branch path. This will still catch most errors. Branch checking could be added in the future. Differential Revision: https://reviews.llvm.org/D104945
69 lines
3.1 KiB
TableGen
69 lines
3.1 KiB
TableGen
//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly instruction format definitions.
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///
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format.
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// We instantiate 2 of these for every actual instruction (register based
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// and stack based), see below.
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class WebAssemblyInst<bits<32> inst, string asmstr, string stack, string is64>
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: StackRel, RegisterRel, Wasm64Rel, Instruction {
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bits<32> Inst = inst; // Instruction encoding.
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string StackBased = stack;
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string BaseName = NAME;
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string IsWasm64 = is64;
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string Wasm32Name = !subst("_A64", "_A32", NAME);
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let Namespace = "WebAssembly";
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let Pattern = [];
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let AsmString = asmstr;
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// When there are multiple instructions that map to the same encoding (in
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// e.g. the disassembler use case) prefer the one where IsCanonical == 1.
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bit IsCanonical = 0;
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}
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// Normal instructions. Default instantiation of a WebAssemblyInst.
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class NI<dag oops, dag iops, list<dag> pattern, string stack,
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string asmstr = "", bits<32> inst = -1, string is64 = "false">
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: WebAssemblyInst<inst, asmstr, stack, is64> {
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dag OutOperandList = oops;
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dag InOperandList = iops;
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let Pattern = pattern;
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let Defs = [ARGUMENTS];
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}
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// Generates both register and stack based versions of one actual instruction.
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// We have 2 sets of operands (oops & iops) for the register and stack
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// based version of this instruction, as well as the corresponding asmstr.
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// The register versions have virtual-register operands which correspond to wasm
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// locals or stack locations. Each use and def of the register corresponds to an
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// implicit local.get / local.set or access of stack operands in wasm. These
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// instructions are used for ISel and all MI passes. The stack versions of the
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// instructions do not have register operands (they implicitly operate on the
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// stack), and local.gets and local.sets are explicit. The register instructions
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// are converted to their corresponding stack instructions before lowering to
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// MC.
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// Every instruction should want to be based on this multi-class to guarantee
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// there is always an equivalent pair of instructions.
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multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
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list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
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bits<32> inst = -1, string is64 = "false"> {
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let isCodeGenOnly = 1 in
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def "" : NI<oops_r, iops_r, pattern_r, "false", asmstr_r, inst, is64>;
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let BaseName = NAME in
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def _S : NI<oops_s, iops_s, [], "true", asmstr_s, inst, is64>;
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}
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// For instructions that have no register ops, so both sets are the same.
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multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
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bits<32> inst = -1> {
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defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
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}
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