adec922361
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.
The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.
On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.
When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.
A lot of existing tests have updated. This is a summary of the important
differences:
- Most changes are the same instructions in a different order.
- Sometimes this leads to very minor inefficiencies, such as requiring
an extra mov to move variables into r0/v0 for the return value of a test
function.
- misched-fusion.ll was no longer fusing the pairs of instructions it
should, as per D110561. I've changed the schedule used in the test
for now.
- neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
the different latencies. This seems fine to me.
- Some SVE tests do not always remove movprfx where they did before due
to different register allocation giving different destructive forms.
- The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
produce two LDR where they previously produced an LDP due to
store-pair-suppress kicking in.
- arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
- Some tests such as arm64-neon-mul-div.ll and
ragreedy-local-interval-cost.ll have more, less or just different
spilling.
- In aarch64_generated_funcs.ll.generated.expected one part of the
function is no longer outlined. Interestingly if I switch this to use
any other scheduled even less is outlined.
Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.
Differential Revision: https://reviews.llvm.org/D110830
225 lines
8.4 KiB
LLVM
225 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-unknown-linux < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=CHECK-APPLE
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; Check CSR split can work properly for tests below.
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@a = common dso_local local_unnamed_addr global i32 0, align 4
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define dso_local signext i32 @test1(i32* %b) local_unnamed_addr {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: adrp x8, a
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; CHECK-NEXT: ldrsw x8, [x8, :lo12:a]
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; CHECK-NEXT: cmp x8, x0
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; CHECK-NEXT: b.eq .LBB0_2
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; CHECK-NEXT: // %bb.1: // %if.end
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; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2: // %if.then
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; CHECK-NEXT: mov x19, x0
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; CHECK-NEXT: bl callVoid
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; CHECK-NEXT: mov x0, x19
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; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: b callNonVoid
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;
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; CHECK-APPLE-LABEL: test1:
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; CHECK-APPLE: ; %bb.0: ; %entry
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; CHECK-APPLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: .cfi_def_cfa_offset 32
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; CHECK-APPLE-NEXT: .cfi_offset w30, -8
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; CHECK-APPLE-NEXT: .cfi_offset w29, -16
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; CHECK-APPLE-NEXT: .cfi_offset w19, -24
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; CHECK-APPLE-NEXT: .cfi_offset w20, -32
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; CHECK-APPLE-NEXT: Lloh0:
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; CHECK-APPLE-NEXT: adrp x8, _a@PAGE
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; CHECK-APPLE-NEXT: Lloh1:
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; CHECK-APPLE-NEXT: ldrsw x8, [x8, _a@PAGEOFF]
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; CHECK-APPLE-NEXT: cmp x8, x0
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; CHECK-APPLE-NEXT: b.eq LBB0_2
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; CHECK-APPLE-NEXT: ; %bb.1: ; %if.end
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; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: ret
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; CHECK-APPLE-NEXT: LBB0_2: ; %if.then
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; CHECK-APPLE-NEXT: mov x19, x0
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; CHECK-APPLE-NEXT: bl _callVoid
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; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: mov x0, x19
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; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: b _callNonVoid
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; CHECK-APPLE-NEXT: .loh AdrpLdr Lloh0, Lloh1
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entry:
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%0 = load i32, i32* @a, align 4, !tbaa !2
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%conv = sext i32 %0 to i64
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%1 = inttoptr i64 %conv to i32*
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%cmp = icmp eq i32* %1, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = tail call signext i32 bitcast (i32 (...)* @callVoid to i32 ()*)()
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%call2 = tail call signext i32 @callNonVoid(i32* %b)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%retval.0 = phi i32 [ %call2, %if.then ], [ undef, %entry ]
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ret i32 %retval.0
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}
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declare signext i32 @callVoid(...) local_unnamed_addr
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declare signext i32 @callNonVoid(i32*) local_unnamed_addr
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define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: cbz x0, .LBB1_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: adrp x8, a
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; CHECK-NEXT: mov x19, x0
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; CHECK-NEXT: ldrsw x8, [x8, :lo12:a]
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; CHECK-NEXT: cmp x8, x0
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; CHECK-NEXT: b.ne .LBB1_3
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; CHECK-NEXT: // %bb.2: // %if.then2
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; CHECK-NEXT: bl callVoid
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; CHECK-NEXT: mov x0, x19
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; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: b callNonVoid
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; CHECK-NEXT: .LBB1_3: // %return
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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;
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; CHECK-APPLE-LABEL: test2:
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; CHECK-APPLE: ; %bb.0: ; %entry
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; CHECK-APPLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: .cfi_def_cfa_offset 32
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; CHECK-APPLE-NEXT: .cfi_offset w30, -8
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; CHECK-APPLE-NEXT: .cfi_offset w29, -16
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; CHECK-APPLE-NEXT: .cfi_offset w19, -24
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; CHECK-APPLE-NEXT: .cfi_offset w20, -32
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; CHECK-APPLE-NEXT: cbz x0, LBB1_3
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; CHECK-APPLE-NEXT: ; %bb.1: ; %entry
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; CHECK-APPLE-NEXT: Lloh2:
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; CHECK-APPLE-NEXT: adrp x8, _a@PAGE
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; CHECK-APPLE-NEXT: mov x19, x0
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; CHECK-APPLE-NEXT: Lloh3:
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; CHECK-APPLE-NEXT: ldrsw x8, [x8, _a@PAGEOFF]
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; CHECK-APPLE-NEXT: cmp x8, x0
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; CHECK-APPLE-NEXT: b.ne LBB1_3
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; CHECK-APPLE-NEXT: ; %bb.2: ; %if.then2
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; CHECK-APPLE-NEXT: bl _callVoid
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; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: mov x0, x19
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; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: b _callNonVoid
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; CHECK-APPLE-NEXT: LBB1_3: ; %return
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; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: mov w0, wzr
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; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: ret
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; CHECK-APPLE-NEXT: .loh AdrpLdr Lloh2, Lloh3
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entry:
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%tobool = icmp eq i32* %p1, null
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br i1 %tobool, label %return, label %if.end
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if.end: ; preds = %entry
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%0 = load i32, i32* @a, align 4, !tbaa !2
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%conv = sext i32 %0 to i64
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%1 = inttoptr i64 %conv to i32*
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%cmp = icmp eq i32* %1, %p1
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br i1 %cmp, label %if.then2, label %return
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if.then2: ; preds = %if.end
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%call = tail call signext i32 bitcast (i32 (...)* @callVoid to i32 ()*)()
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%call3 = tail call signext i32 @callNonVoid(i32* nonnull %p1)
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br label %return
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return: ; preds = %if.end, %entry, %if.then2
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%retval.0 = phi i32 [ %call3, %if.then2 ], [ 0, %entry ], [ 0, %if.end ]
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ret i32 %retval.0
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}
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define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_addr {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill
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; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: .cfi_offset w30, -32
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; CHECK-NEXT: ldr x19, [x0]
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; CHECK-NEXT: cbz x19, .LBB2_2
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; CHECK-NEXT: // %bb.1: // %land.rhs
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; CHECK-NEXT: mov x20, x0
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; CHECK-NEXT: mov x0, x19
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; CHECK-NEXT: bl bar
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; CHECK-NEXT: str x0, [x20]
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; CHECK-NEXT: .LBB2_2: // %land.end
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; CHECK-NEXT: mov x0, x19
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; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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;
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; CHECK-APPLE-LABEL: test3:
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; CHECK-APPLE: ; %bb.0: ; %entry
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; CHECK-APPLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
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; CHECK-APPLE-NEXT: .cfi_def_cfa_offset 32
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; CHECK-APPLE-NEXT: .cfi_offset w30, -8
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; CHECK-APPLE-NEXT: .cfi_offset w29, -16
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; CHECK-APPLE-NEXT: .cfi_offset w19, -24
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; CHECK-APPLE-NEXT: .cfi_offset w20, -32
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; CHECK-APPLE-NEXT: ldr x19, [x0]
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; CHECK-APPLE-NEXT: cbz x19, LBB2_2
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; CHECK-APPLE-NEXT: ; %bb.1: ; %land.rhs
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; CHECK-APPLE-NEXT: mov x20, x0
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; CHECK-APPLE-NEXT: mov x0, x19
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; CHECK-APPLE-NEXT: bl _bar
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; CHECK-APPLE-NEXT: str x0, [x20]
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; CHECK-APPLE-NEXT: LBB2_2: ; %land.end
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; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: mov x0, x19
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; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
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; CHECK-APPLE-NEXT: ret
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entry:
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%0 = load i8*, i8** %p1, align 8, !tbaa !6
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%tobool = icmp eq i8* %0, null
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br i1 %tobool, label %land.end, label %land.rhs
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land.rhs: ; preds = %entry
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%call = tail call i8* @bar(i8* nonnull %0, i8 zeroext %p2)
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store i8* %call, i8** %p1, align 8, !tbaa !6
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br label %land.end
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land.end: ; preds = %entry, %land.rhs
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ret i8* %0
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}
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declare i8* @bar(i8*, i8 zeroext) local_unnamed_addr
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!llvm.module.flags = !{!0}
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!llvm.ident = !{!1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!"clang version 10.0.0 (trunk 367381) (llvm/trunk 367388)"}
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!2 = !{!3, !3, i64 0}
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!3 = !{!"int", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!7, !7, i64 0}
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!7 = !{!"any pointer", !4, i64 0}
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