adec922361
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.
The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.
On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.
When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.
A lot of existing tests have updated. This is a summary of the important
differences:
- Most changes are the same instructions in a different order.
- Sometimes this leads to very minor inefficiencies, such as requiring
an extra mov to move variables into r0/v0 for the return value of a test
function.
- misched-fusion.ll was no longer fusing the pairs of instructions it
should, as per D110561. I've changed the schedule used in the test
for now.
- neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
the different latencies. This seems fine to me.
- Some SVE tests do not always remove movprfx where they did before due
to different register allocation giving different destructive forms.
- The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
produce two LDR where they previously produced an LDP due to
store-pair-suppress kicking in.
- arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
- Some tests such as arm64-neon-mul-div.ll and
ragreedy-local-interval-cost.ll have more, less or just different
spilling.
- In aarch64_generated_funcs.ll.generated.expected one part of the
function is no longer outlined. Interestingly if I switch this to use
any other scheduled even less is outlined.
Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.
Differential Revision: https://reviews.llvm.org/D110830
428 lines
11 KiB
LLVM
428 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -O3 -mtriple=aarch64-unknown-unknown -enable-implicit-null-checks | FileCheck %s
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; Basic test for implicit null check conversion - this is analogous to the
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; file with the same name in the X86 tree, but adjusted to remove patterns
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; related to memory folding of arithmetic (since aarch64 doesn't), and add
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; a couple of aarch64 specific tests.
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define i32 @imp_null_check_load_fallthrough(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fallthrough:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB0_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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not_null:
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%t = load i32, i32* %x
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ret i32 %t
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is_null:
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ret i32 42
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}
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define i32 @imp_null_check_load_reorder(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_reorder:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB1_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load i32, i32* %x
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ret i32 %t
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}
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define i32 @imp_null_check_unordered_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_unordered_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp2:
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; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB2_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load atomic i32, i32* %x unordered, align 4
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ret i32 %t
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}
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; TODO: Can be converted into implicit check.
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;; Probably could be implicit, but we're conservative for now
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define i32 @imp_null_check_seq_cst_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_seq_cst_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB3_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldar w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load atomic i32, i32* %x seq_cst, align 4
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ret i32 %t
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}
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;; Might be memory mapped IO, so can't rely on fault behavior
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define i32 @imp_null_check_volatile_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_volatile_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB4_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load volatile i32, i32* %x, align 4
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ret i32 %t
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}
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define i8 @imp_null_check_load_i8(i8* %x) {
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; CHECK-LABEL: imp_null_check_load_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp3:
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; CHECK-NEXT: ldrb w0, [x0] // on-fault: .LBB5_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i8* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i8 42
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not_null:
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%t = load i8, i8* %x
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ret i8 %t
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}
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define i256 @imp_null_check_load_i256(i256* %x) {
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; CHECK-LABEL: imp_null_check_load_i256:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB6_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldp x2, x3, [x0, #16]
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; CHECK-NEXT: ldp x0, x1, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: mov x1, xzr
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; CHECK-NEXT: mov x2, xzr
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; CHECK-NEXT: mov x3, xzr
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i256* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i256 42
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not_null:
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%t = load i256, i256* %x
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ret i256 %t
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}
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define i32 @imp_null_check_gep_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_gep_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp4:
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; CHECK-NEXT: ldr w0, [x0, #128] // on-fault: .LBB7_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.gep = getelementptr i32, i32* %x, i32 32
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%t = load i32, i32* %x.gep
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ret i32 %t
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}
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define i32 @imp_null_check_add_result(i32* %x, i32 %p) {
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; CHECK-LABEL: imp_null_check_add_result:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp5:
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; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB8_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB8_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t = load i32, i32* %x
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%p1 = add i32 %t, %p
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ret i32 %p1
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}
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; Can hoist over a potential faulting instruction as long as we don't
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; change the conditions under which the instruction faults.
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define i32 @imp_null_check_hoist_over_udiv(i32* %x, i32 %a, i32 %b) {
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; CHECK-LABEL: imp_null_check_hoist_over_udiv:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB9_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: udiv w8, w1, w2
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; CHECK-NEXT: ldr w9, [x0]
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; CHECK-NEXT: add w0, w9, w8
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB9_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%p1 = udiv i32 %a, %b
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%t = load i32, i32* %x
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%res = add i32 %t, %p1
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ret i32 %res
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}
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; TODO: We should be able to hoist this - we can on x86, why isn't this
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; working for aarch64? Aliasing?
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define i32 @imp_null_check_hoist_over_unrelated_load(i32* %x, i32* %y, i32* %z) {
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; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB10_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB10_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%t0 = load i32, i32* %y
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%t1 = load i32, i32* %x
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store i32 %t0, i32* %z
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ret i32 %t1
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}
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define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) {
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; CHECK-LABEL: imp_null_check_gep_load_with_use_dep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp6:
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; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB11_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: add w9, w0, w1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w0, w8, #4
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB11_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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%x.loc = getelementptr i32, i32* %x, i32 1
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%y = ptrtoint i32* %x.loc to i32
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%b = add i32 %a, %y
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%t = load i32, i32* %x
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%z = add i32 %t, %b
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ret i32 %z
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}
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;; TODO: We could handle this case as we can lift the fence into the
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;; previous block before the conditional without changing behavior.
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define i32 @imp_null_check_load_fence1(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fence1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB12_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB12_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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fence acquire
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%t = load i32, i32* %x
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ret i32 %t
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}
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;; TODO: We could handle this case as we can lift the fence into the
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;; previous block before the conditional without changing behavior.
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define i32 @imp_null_check_load_fence2(i32* %x) {
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; CHECK-LABEL: imp_null_check_load_fence2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB13_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldr w0, [x0]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB13_2:
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; CHECK-NEXT: mov w0, #42
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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fence seq_cst
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%t = load i32, i32* %x
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ret i32 %t
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}
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; TODO: We can fold to implicit null here, not sure why this isn't working
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define void @imp_null_check_store(i32* %x) {
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; CHECK-LABEL: imp_null_check_store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB14_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: .LBB14_2: // %common.ret
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret void
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not_null:
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store i32 1, i32* %x
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ret void
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}
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;; TODO: can be implicit
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define void @imp_null_check_unordered_store(i32* %x) {
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; CHECK-LABEL: imp_null_check_unordered_store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cbz x0, .LBB15_2
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; CHECK-NEXT: // %bb.1: // %not_null
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: .LBB15_2: // %common.ret
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; CHECK-NEXT: ret
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entry:
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%c = icmp eq i32* %x, null
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br i1 %c, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret void
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not_null:
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store atomic i32 1, i32* %x unordered, align 4
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ret void
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}
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define i32 @imp_null_check_neg_gep_load(i32* %x) {
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; CHECK-LABEL: imp_null_check_neg_gep_load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: .Ltmp7:
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; CHECK-NEXT: ldur w0, [x0, #-128] // on-fault: .LBB16_2
|
|
; CHECK-NEXT: // %bb.1: // %not_null
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB16_2:
|
|
; CHECK-NEXT: mov w0, #42
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%c = icmp eq i32* %x, null
|
|
br i1 %c, label %is_null, label %not_null, !make.implicit !0
|
|
|
|
is_null:
|
|
ret i32 42
|
|
|
|
not_null:
|
|
%x.gep = getelementptr i32, i32* %x, i32 -32
|
|
%t = load i32, i32* %x.gep
|
|
ret i32 %t
|
|
}
|
|
|
|
!0 = !{}
|