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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper fe1f0de003 [RISCV][WebAssembly][TargetLowering] Allow expandCTLZ/expandCTTZ to rely on CTPOP expansion for vectors. 
Our fallback expansion for CTLZ/CTTZ relies on CTPOP. If CTPOP
isn't legal or custom for a vector type we would scalarize the
CTLZ/CTTZ. This is different than CTPOP itself which would use a
vector expansion.

This patch teaches expandCTLZ/CTTZ to rely on the vector CTPOP
expansion instead of scalarizing. To do this I had to add additional
checks to make sure the operations used by CTPOP expansions are all
supported. Some of the operations were already needed for the CTLZ/CTTZ
expansion.

This is a huge improvement to the RISCV which doesn't have a scalar
ctlz or cttz in the base ISA.

For WebAssembly, I've added Custom lowering to keep the scalarizing
behavior. I've also extended the scalarizing to CTPOP.

Differential Revision: https://reviews.llvm.org/D111919
2021-10-20 07:46:41 -07:00
..
GlobalISel
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
intrinsics
…
rvv
[RISCV][WebAssembly][TargetLowering] Allow expandCTLZ/expandCTTZ to rely on CTPOP expansion for vectors.
2021-10-20 07:46:41 -07:00
add-before-shl.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
add-imm.ll
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV][test] Add more tests of (add (mul r, c0), c1)
2021-10-08 01:26:29 +00:00
addrspacecast.ll
…
aext-to-sext.ll
[RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being called for an illegal i32 shift amount.
2021-06-29 09:45:13 -07:00
align-loops.ll
[CodeGen] Add -align-loops
2021-08-04 12:45:18 -07:00
align.ll
…
alloca.ll
…
alu8.ll
Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
2021-06-27 10:33:43 -07:00
alu16.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
alu32.ll
[RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.
2021-08-26 10:20:19 -07:00
alu64.ll
…
analyze-branch.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
atomic-signext.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
attributes.ll
[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.
2021-10-14 09:25:03 -07:00
blockaddress.ll
…
branch-relaxation.ll
…
branch.ll
[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Add another isel optimization for (and (shl X, c2), c1).
2021-09-24 15:10:25 -07:00
byval.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll
…
callee-saved-fpr64s.ll
…
callee-saved-gprs.ll
…
calling-conv-half.ll
[RISCV] Improve constant materialization for stores of i16 or i32 negative constants.
2021-08-18 10:25:12 -07:00
calling-conv-ilp32-ilp32f-common.ll
…
calling-conv-ilp32-ilp32f-ilp32d-common.ll
…
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
…
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
…
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Fix a crash when lowering split float arguments
2021-07-22 09:55:26 +01:00
calls.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
…
compress-float.ll
…
compress-inline-asm.ll
…
compress.ll
…
copy-frameindex.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
copysign-casts.ll
[RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.
2021-08-26 10:20:19 -07:00
disable-tail-calls.ll
…
disjoint.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
div.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
double-arith.ll
…
double-bitmanip-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
double-br-fcmp.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
double-calling-conv.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
double-convert.ll
[RISCV] Remove stale FIXMEs from float-convert.ll and double-convert.ll. NFC
2021-09-22 14:25:40 -07:00
double-fcmp.ll
…
double-frem.ll
…
double-imm.ll
…
double-intrinsics.ll
[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
2021-07-06 11:43:22 -07:00
double-isnan.ll
…
double-mem.ll
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
2021-07-20 09:22:06 -07:00
double-previous-failure.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
double-select-fcmp.ll
…
double-stack-spill-restore.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
dwarf-eh.ll
…
elf-preemption.ll
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-11 11:29:45 -07:00
exception-pointer-register.ll
…
fastcc-float.ll
[RISCV] Fix a crash when lowering split float arguments
2021-07-22 09:55:26 +01:00
fastcc-int.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
fixups-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
float-arith.ll
…
float-bit-preserving-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
float-convert.ll
[RISCV] Remove stale FIXMEs from float-convert.ll and double-convert.ll. NFC
2021-09-22 14:25:40 -07:00
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
…
float-intrinsics.ll
[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
2021-07-06 11:43:22 -07:00
float-isnan.ll
…
float-mem.ll
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
2021-07-20 09:22:06 -07:00
float-select-fcmp.ll
…
flt-rounds.ll
…
fold-addi-loadstore.ll
…
fp16-promote.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
fp128.ll
…
fp-imm.ll
…
fpenv.ll
[RISCV] Custom lowering of SET_ROUNDING
2021-04-22 15:04:55 +07:00
frame-info.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
frame.ll
…
frameaddr-returnaddr.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
half-arith.ll
…
half-bitmanip-dagcombines.ll
[RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64.
2021-08-08 18:30:48 -07:00
half-br-fcmp.ll
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
half-convert.ll
[RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers
2021-09-22 14:24:26 -07:00
half-fcmp.ll
…
half-imm.ll
…
half-intrinsics.ll
[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
2021-07-06 11:43:22 -07:00
half-isnan.ll
…
half-mem.ll
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
2021-07-20 09:22:06 -07:00
half-select-fcmp.ll
…
hoist-global-addr-base.ll
[RISCV] Add riscv64 command line to hoist-global-addr-base.ll. NFC
2021-10-04 17:01:59 -07:00
i32-icmp.ll
…
imm-cse.ll
…
imm.ll
[RISCV] Optimize immediate materialisation with SH*ADD
2021-10-15 06:46:41 +00:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-S-constraint.ll
[RISCV] Support machine constraint "S"
2021-07-13 09:30:09 -07:00
inline-asm.ll
…
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
…
jumptable.ll
[CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt.
2021-06-23 15:38:11 -07:00
large-stack.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
legalize-fneg.ll
…
lit.local.cfg
…
lsr-legaladdimm.ll
…
machineoutliner-jumptable.mir
[RISCV] Fix Machine Outliner jump table handling.
2021-09-09 07:32:30 +02:00
machineoutliner.mir
…
mattr-invalid-combination.ll
…
mem64.ll
…
mem.ll
…
mir-target-flags.ll
…
module-target-abi2.ll
…
module-target-abi.ll
…
mul.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
musttail-call.ll
…
neg-abs.ll
…
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
2021-08-31 11:23:56 -07:00
patchable-function-entry.ll
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
2021-05-29 15:11:37 +01:00
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.
2021-07-28 09:05:45 -07:00
prefetch.ll
…
readcyclecounter.ll
…
rem.ll
[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)
2021-07-20 08:53:55 -07:00
remat.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
rv32zba.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbb-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbb-zbp.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbb.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbc-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbe-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbp-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbp.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv32zbs.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv32zbt.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64-large-stack.ll
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
2021-07-20 09:22:06 -07:00
rv64d-double-convert.ll
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
2021-07-24 10:50:43 -07:00
rv64f-float-convert.ll
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
2021-07-24 10:50:43 -07:00
rv64f-half-convert.ll
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
2021-07-24 10:50:43 -07:00
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
rv64i-single-softfloat.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll
…
rv64zba.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbb-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbb-zbp.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbb.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbc-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbe-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbp-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbp.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv64zbs.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbt.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
sadd_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
sadd_sat.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
saverestore.ll
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
2021-08-10 09:02:56 -07:00
select-cc.ll
[RISCV] Support RISCVISD::SELECT_CC in ComputeNumSignBitsForTargetNode.
2021-08-13 18:00:09 -07:00
select-const.ll
…
select-constant-xor.ll
[DAG] Fix GT -> GE condition when creating SetCC
2021-09-08 12:41:51 +01:00
select-optimize-multiple.ll
…
select-optimize-multiple.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
select-or.ll
…
setcc-logic.ll
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll
…
shadowcallstack.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
shift-and.ll
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
shifts.ll
[SelectionDAG] Fix shift libcall ABI mismatch in shift-amount argument
2021-10-08 09:57:57 +08:00
shlimm-addimm.ll
[RISCV][test] Add tests of (add (shl r, c0), c1)
2021-10-14 14:53:03 +00:00
shrinkwrap.ll
[RISCV] Improve shrink wrap test (NFC)
2021-09-02 12:14:04 -05:00
spill-fpr-scalar.ll
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
2021-07-23 09:12:05 -07:00
split-offsets.ll
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
2021-08-18 10:44:25 -07:00
split-sp-adjust.ll
…
srem-lkk.ll
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
srem-seteq-illegal-types.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
srem-vector-lkk.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
ssub_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
ssub_sat.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
stack-slot-size.ll
[RISCV] Fix stack slot for argument types (Bug 49500)
2021-04-29 09:10:48 +01:00
stack-store-check.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
subtarget-features-std-ext.ll
…
tail-calls.ll
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
2021-07-13 09:46:21 -07:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
uadd_sat_plus.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
uadd_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
umulo-128-legalisation-lowering.ll
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
2021-08-31 11:23:56 -07:00
urem-lkk.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
urem-seteq-illegal-types.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
urem-vector-lkk.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
usub_sat_plus.ll
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
2021-08-18 10:22:00 -07:00
usub_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
vararg.ll
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
2021-08-18 10:44:25 -07:00
vec3-setcc-crash.ll
Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
2021-06-27 10:33:43 -07:00
vector-abi.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
verify-instr.mir
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wide-mem.ll
…
xaluo.ll
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
2021-08-31 11:23:56 -07:00
zext-with-load-is-free.ll
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zfh-imm.ll
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