85c53c7092
It caused builds to assert with:
(StackSize == 0 && "We already have the CFA offset!"),
function generateCompactUnwindEncoding, file AArch64AsmBackend.cpp, line 624.
when targeting iOS. See comment on the code review for reproducer.
> This patch rearranges emission of CFI instructions, so the resulting
> DWARF and `.eh_frame` information is precise at every instruction.
>
> The current state is that the unwind info is emitted only after the
> function prologue. This is fine for synchronous (e.g. C++) exceptions,
> but the information is generally incorrect when the program counter is
> at an instruction in the prologue or the epilogue, for example:
>
> ```
> stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
> mov x29, sp
> .cfi_def_cfa w29, 16
> ...
> ```
>
> after the `stp` is executed the (initial) rule for the CFA still says
> the CFA is in the `sp`, even though it's already offset by 16 bytes
>
> A correct unwind info could look like:
> ```
> stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
> .cfi_def_cfa_offset 16
> mov x29, sp
> .cfi_def_cfa w29, 16
> ...
> ```
>
> Having this information precise up to an instruction is useful for
> sampling profilers that would like to get a stack backtrace. The end
> goal (towards this patch is just a step) is to have fully working
> `-fasynchronous-unwind-tables`.
>
> Reviewed By: danielkiss, MaskRay
>
> Differential Revision: https://reviews.llvm.org/D111411
This reverts commit 32e8b550e5.
86 lines
3.5 KiB
LLVM
86 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-darwin -debug-entry-values -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -debug-entry-values -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
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; Trivial patchpoint codegen
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;
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define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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; CHECK-LABEL: trivial_patchpoint_codegen:
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; CHECK: mov x16, #244834610708480
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; CHECK-NEXT: movk x16, #48879, lsl #16
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; CHECK-NEXT: movk x16, #51966
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; CHECK-NEXT: blr x16
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; CHECK: mov x16, #244834610708480
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; CHECK-NEXT: movk x16, #48879, lsl #16
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; CHECK-NEXT: movk x16, #51967
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; CHECK-NEXT: blr x16
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; CHECK: ret
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%resolveCall2 = inttoptr i64 244837814094590 to i8*
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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%resolveCall3 = inttoptr i64 244837814094591 to i8*
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
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ret i64 %result
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}
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; Caller frame metadata with stackmaps. This should not be optimized
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; as a leaf function.
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;
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; CHECK-LABEL: caller_meta_leaf
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; CHECK: sub sp, sp, #48
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; CHECK-NEXT: stp x29, x30, [sp, #32]
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; CHECK-NEXT: add x29, sp, #32
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; CHECK: Ltmp
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; CHECK: add sp, sp, #48
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; CHECK: ret
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define void @caller_meta_leaf() {
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entry:
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%metadata = alloca i64, i32 3, align 8
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store i64 11, i64* %metadata
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store i64 12, i64* %metadata
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store i64 13, i64* %metadata
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call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
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ret void
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}
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; Test patchpoints reusing the same TargetConstant.
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; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
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; There is no way to verify this, since it depends on memory allocation.
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; But I think it's useful to include as a working example.
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define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
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entry:
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%tmp80 = add i64 %tmp79, -16
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%tmp81 = inttoptr i64 %tmp80 to i64*
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%tmp82 = load i64, i64* %tmp81, align 8
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
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%tmp83 = load i64, i64* %tmp33, align 8
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%tmp84 = add i64 %tmp83, -24
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%tmp85 = inttoptr i64 %tmp84 to i64*
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%tmp86 = load i64, i64* %tmp85, align 8
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
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ret i64 10
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}
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; Test small patchpoints that don't emit calls.
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define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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; CHECK-LABEL: small_patchpoint_codegen:
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; CHECK: Ltmp
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; CHECK: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: ldp
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; CHECK-NEXT: ret
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
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ret void
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}
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declare void @llvm.experimental.stackmap(i64, i32, ...)
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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