cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
105 lines
4.0 KiB
LLVM
105 lines
4.0 KiB
LLVM
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; The goal of this test is to voluntarily create 2 overlapping convergence
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; structures: the loop, and the inner condition.
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; Here, the condition header also branches to 2 internal nodes, which are not
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; directly a merge/exits.
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; This will require a proper header-split.
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; In addition, splitting the header makes the continue the merge of the inner
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; condition, so we need to properly split the continue block to create a
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; valid inner merge, in the correct order.
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; CHECK-DAG: OpName %[[#switch_0:]] "reg1"
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; CHECK-DAG: OpName %[[#variable:]] "var"
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; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0
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; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1
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; CHECK-DAG: %[[#int_2:]] = OpConstant %[[#]] 2
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; CHECK-DAG: %[[#int_3:]] = OpConstant %[[#]] 3
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; CHECK-DAG: %[[#int_4:]] = OpConstant %[[#]] 4
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define internal spir_func void @main() #1 {
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; CHECK: %[[#entry:]] = OpLabel
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; CHECK: %[[#switch_0]] = OpVariable %[[#]] Function
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; CHECK: %[[#variable]] = OpVariable %[[#]] Function
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; CHECK: OpBranch %[[#header:]]
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%var = alloca i32, align 4
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br label %header
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; CHECK: %[[#header]] = OpLabel
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; CHECK: OpLoopMerge %[[#merge:]] %[[#continue:]] None
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; CHECK: OpBranch %[[#split_header:]]
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; CHECK: %[[#split_header]] = OpLabel
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; CHECK: OpSelectionMerge %[[#inner_merge:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]]
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header:
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%2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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br i1 true, label %left, label %right
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; CHECK: %[[#left]] = OpLabel
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; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]]
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; CHECK-DAG: OpStore %[[#variable]] %[[#int_1]]
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; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#left_next:]]
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left:
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store i32 1, ptr %var
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br i1 true, label %merge, label %left_next
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; CHECK: %[[#right]] = OpLabel
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; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]]
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; CHECK-DAG: OpStore %[[#variable]] %[[#int_2]]
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; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#right_next:]]
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right:
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store i32 2, ptr %var
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br i1 true, label %merge, label %right_next
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; CHECK: %[[#left_next]] = OpLabel
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; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]]
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; CHECK-DAG: OpStore %[[#variable]] %[[#int_3]]
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; CHECK: OpBranch %[[#inner_merge]]
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left_next:
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store i32 3, ptr %var
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br label %continue
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; CHECK: %[[#right_next]] = OpLabel
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; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]]
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; CHECK-DAG: OpStore %[[#variable]] %[[#int_4]]
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; CHECK: OpBranch %[[#inner_merge]]
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right_next:
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store i32 4, ptr %var
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br label %continue
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; CHECK: %[[#inner_merge]] = OpLabel
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; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]]
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; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]]
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; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#continue]]
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; CHECK: %[[#continue]] = OpLabel
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; CHECK: OpBranch %[[#header]]
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continue:
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br label %header
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; CHECK: %[[#merge]] = OpLabel
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; CHECK: OpReturn
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merge:
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ret void
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}
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declare token @llvm.experimental.convergence.entry() #0
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declare token @llvm.experimental.convergence.loop() #0
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attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #1 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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