5b0572875c
MSVC linker accepts native ARM64 object files as input with `-machine:arm64ec`, similar to `-machine:arm64x`. Its usefulness is very limited; for example, both exports and imports are not reflected in the PE structures and can't work. However, their symbol tables are otherwise functional. Since we already have handling of multiple symbol tables implemented for ARM64X, the required changes are mostly about adjusting relevant checks to account for them on the ARM64EC target. Delay-load helper handling is a bit of a shortcut. The patch never pulls it for native object files and just ensures that the code is fine with that. In general, I think it would be nice to adjust the driver to pull it only when it's actually referenced, which would allow applying the same logic to the native symbol table on ARM64EC without worrying about pulling too much.
193 lines
7.4 KiB
ArmAsm
193 lines
7.4 KiB
ArmAsm
# REQUIRES: aarch64, x86
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# RUN: split-file %s %t.dir && cd %t.dir
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# RUN: llvm-mc -filetype=obj -triple=arm64ec-windows funcs.s -o funcs-arm64ec.obj
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# RUN: llvm-mc -filetype=obj -triple=aarch64-windows native-funcs.s -o funcs-aarch64.obj
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# RUN: llvm-mc -filetype=obj -triple=x86_64-windows space.s -o space-x86_64.obj
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# RUN: llvm-mc -filetype=obj -triple=aarch64-windows space.s -o space-aarch64.obj
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# RUN: llvm-mc -filetype=obj -triple=aarch64-windows %S/Inputs/loadconfig-arm64.s -o loadconfig-arm64.obj
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# RUN: llvm-mc -filetype=obj -triple=arm64ec-windows %S/Inputs/loadconfig-arm64ec.s -o loadconfig-arm64ec.obj
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# Test generating range extension thunks for ARM64EC code. Place some x86_64 chunks in a middle
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# and make sure that thunks stay in ARM64EC code range.
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# RUN: lld-link -machine:arm64ec -noentry -dll funcs-arm64ec.obj space-x86_64.obj loadconfig-arm64ec.obj -out:test.dll \
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# RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
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# VERBOSE: Added 3 thunks with margin {{.*}} in 1 passes
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# RUN: llvm-objdump -d test.dll | FileCheck --check-prefix=DISASM %s
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# DISASM: Disassembly of section .code1:
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# DISASM-EMPTY:
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# DISASM-NEXT: 0000000180004000 <.code1>:
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# DISASM-NEXT: 180004000: 36000040 tbz w0, #0x0, 0x180004008 <.code1+0x8>
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# DISASM-NEXT: 180004004: d65f03c0 ret
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# DISASM-NEXT: 180004008: b0000050 adrp x16, 0x18000d000
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# DISASM-NEXT: 18000400c: 91000210 add x16, x16, #0x0
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# DISASM-NEXT: 180004010: d61f0200 br x16
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# DISASM-EMPTY:
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# DISASM-NEXT: Disassembly of section .code2:
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# DISASM-EMPTY:
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# DISASM-NEXT: 0000000180005000 <.code2>:
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# DISASM-NEXT: ...
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# DISASM-EMPTY:
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# DISASM-NEXT: Disassembly of section .code3:
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# DISASM-EMPTY:
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# DISASM-NEXT: 0000000180006000 <.code3>:
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# DISASM-NEXT: ...
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# DISASM-NEXT: 18000d000: 36000060 tbz w0, #0x0, 0x18000d00c <.code3+0x700c>
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# DISASM-NEXT: 18000d004: d65f03c0 ret
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# DISASM-NEXT: 18000d008: 00000000 udf #0x0
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# DISASM-NEXT: 18000d00c: 90000050 adrp x16, 0x180015000 <.code3+0xf000>
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# DISASM-NEXT: 18000d010: 91006210 add x16, x16, #0x18
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# DISASM-NEXT: 18000d014: d61f0200 br x16
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# DISASM-NEXT: ...
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# DISASM-NEXT: 180015018: 36000040 tbz w0, #0x0, 0x180015020 <.code3+0xf020>
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# DISASM-NEXT: 18001501c: d65f03c0 ret
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# DISASM-NEXT: 180015020: f0ffff70 adrp x16, 0x180004000 <.code1>
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# DISASM-NEXT: 180015024: 91000210 add x16, x16, #0x0
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# DISASM-NEXT: 180015028: d61f0200 br x16
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# RUN: llvm-readobj --coff-load-config test.dll | FileCheck --check-prefix=LOADCFG %s
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# LOADCFG: CodeMap [
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# LOADCFG-NEXT: 0x4000 - 0x4014 ARM64EC
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# LOADCFG-NEXT: 0x5000 - 0x5300 X64
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# LOADCFG-NEXT: 0x6000 - 0x1502C ARM64EC
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# LOADCFG-NEXT: ]
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# A similar test using a hybrid binary and native placeholder chunks.
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# RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj space-aarch64.obj loadconfig-arm64.obj loadconfig-arm64ec.obj \
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# RUN: -out:testx.dll -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
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# RUN: llvm-objdump -d testx.dll | FileCheck --check-prefix=DISASM %s
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# RUN: llvm-readobj --coff-load-config testx.dll | FileCheck --check-prefix=LOADCFGX %s
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# LOADCFGX: CodeMap [
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# LOADCFGX-NEXT: 0x4000 - 0x4014 ARM64EC
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# LOADCFGX-NEXT: 0x5000 - 0x5300 ARM64
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# LOADCFGX-NEXT: 0x6000 - 0x1502C ARM64EC
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# LOADCFGX-NEXT: ]
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# Test a hybrid ARM64X binary which requires range extension thunks for both native and EC relocations.
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# RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj funcs-aarch64.obj loadconfig-arm64.obj loadconfig-arm64ec.obj \
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# RUN: -out:testx2.dll -verbose 2>&1 | FileCheck -check-prefix=VERBOSEX %s
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# VERBOSEX: Added 5 thunks with margin {{.*}} in 1 passes
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# RUN: lld-link -machine:arm64ec -noentry -dll funcs-arm64ec.obj funcs-aarch64.obj loadconfig-arm64.obj loadconfig-arm64ec.obj \
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# RUN: -out:testx2ec.dll -verbose 2>&1 | FileCheck -check-prefix=VERBOSEX %s
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# RUN: llvm-objdump -d testx2.dll | FileCheck --check-prefix=DISASMX %s
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# RUN: llvm-objdump -d testx2ec.dll | FileCheck --check-prefix=DISASMX %s
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# DISASMX: Disassembly of section .code1:
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# DISASMX-EMPTY:
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# DISASMX-NEXT: 0000000180004000 <.code1>:
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# DISASMX-NEXT: 180004000: 36000040 tbz w0, #0x0, 0x180004008 <.code1+0x8>
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# DISASMX-NEXT: 180004004: d65f03c0 ret
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# DISASMX-NEXT: 180004008: b0000050 adrp x16, 0x18000d000
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# DISASMX-NEXT: 18000400c: 91000210 add x16, x16, #0x0
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# DISASMX-NEXT: 180004010: d61f0200 br x16
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# DISASMX-EMPTY:
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# DISASMX-NEXT: Disassembly of section .code2:
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# DISASMX-EMPTY:
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# DISASMX-NEXT: 0000000180005000 <.code2>:
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# DISASMX-NEXT: 180005000: 36000040 tbz w0, #0x0, 0x180005008 <.code2+0x8>
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# DISASMX-NEXT: 180005004: d65f03c0 ret
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# DISASMX-NEXT: 180005008: b0000090 adrp x16, 0x180016000
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# DISASMX-NEXT: 18000500c: 91000210 add x16, x16, #0x0
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# DISASMX-NEXT: 180005010: d61f0200 br x16
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# DISASMX-EMPTY:
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# DISASMX-NEXT: Disassembly of section .code3:
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# DISASMX-EMPTY:
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# DISASMX-NEXT: 0000000180006000 <.code3>:
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# DISASMX-NEXT: ...
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# DISASMX-NEXT: 18000d000: 36000060 tbz w0, #0x0, 0x18000d00c <.code3+0x700c>
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# DISASMX-NEXT: 18000d004: d65f03c0 ret
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# DISASMX-NEXT: 18000d008: 00000000 udf #0x0
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# DISASMX-NEXT: 18000d00c: 90000050 adrp x16, 0x180015000 <.code3+0xf000>
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# DISASMX-NEXT: 18000d010: 91006210 add x16, x16, #0x18
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# DISASMX-NEXT: 18000d014: d61f0200 br x16
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# DISASMX-NEXT: ...
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# DISASMX-NEXT: 180015018: 36000040 tbz w0, #0x0, 0x180015020 <.code3+0xf020>
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# DISASMX-NEXT: 18001501c: d65f03c0 ret
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# DISASMX-NEXT: 180015020: f0ffff70 adrp x16, 0x180004000 <.code1>
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# DISASMX-NEXT: 180015024: 91000210 add x16, x16, #0x0
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# DISASMX-NEXT: 180015028: d61f0200 br x16
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# DISASMX-EMPTY:
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# DISASMX-NEXT: Disassembly of section .code4:
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# DISASMX-EMPTY:
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# DISASMX-NEXT: 0000000180016000 <.code4>:
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# DISASMX-NEXT: 180016000: 36000040 tbz w0, #0x0, 0x180016008 <.code4+0x8>
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# DISASMX-NEXT: 180016004: d65f03c0 ret
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# DISASMX-NEXT: 180016008: f0ffff70 adrp x16, 0x180005000 <.code2>
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# DISASMX-NEXT: 18001600c: 91000210 add x16, x16, #0x0
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# DISASMX-NEXT: 180016010: d61f0200 br x16
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# RUN: llvm-readobj --coff-load-config testx2.dll | FileCheck --check-prefix=LOADCFGX2 %s
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# RUN: llvm-readobj --coff-load-config testx2ec.dll | FileCheck --check-prefix=LOADCFGX2 %s
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# LOADCFGX2: CodeMap [
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# LOADCFGX2-NEXT: 0x4000 - 0x4014 ARM64EC
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# LOADCFGX2-NEXT: 0x5000 - 0x5014 ARM64
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# LOADCFGX2-NEXT: 0x6000 - 0x1502C ARM64EC
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# LOADCFGX2-NEXT: 0x16000 - 0x16014 ARM64
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# LOADCFGX2-NEXT: ]
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#--- funcs.s
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.globl main
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.globl func1
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.globl func2
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.section .code1, "xr"
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main:
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tbz w0, #0, func1
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ret
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.section .code3$a, "xr"
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.space 0x7000
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.section .code3$b, "xr"
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func1:
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tbz w0, #0, func2
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ret
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.space 1
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.section .code3$c, "xr"
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.space 0x8000
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.section .code3$d, "xr"
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.align 2
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func2:
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tbz w0, #0, main
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ret
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#--- space.s
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.section .code2$a, "xr"
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.space 0x100
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.section .code2$b, "xr"
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.space 0x100
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.section .code2$c, "xr"
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.space 0x100
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#--- native-funcs.s
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.globl nmain
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.globl nfunc
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.section .code2, "xr"
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nmain:
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tbz w0, #0, nfunc
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ret
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.section .code4, "xr"
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.align 2
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nfunc:
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tbz w0, #0, nmain
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ret
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