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clang-p2996/llvm/lib/Target/RISCV
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Luís Marques 0d47c7aba3 [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook 
Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint`
hook. The test could check for instruction reorderings, but to avoid
being brittle it just checks instruction dependencies.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67046
2019-11-05 09:39:06 +00:00
..
AsmParser
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
Disassembler
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
MCTargetDesc
[Mips] Use appropriate private label prefix based on Mips ABI
2019-10-23 12:24:35 +02:00
TargetInfo
Revert CMake: Make most target symbols hidden by default
2019-06-11 03:21:13 +00:00
Utils
[RISCV] Add MachineInstr immediate verification
2019-10-16 15:06:02 +00:00
CMakeLists.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
LLVMBuild.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.td
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVAsmPrinter.cpp
[RISCV] Support z and i operand modifiers
2019-07-08 05:00:26 +00:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallLowering.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVExpandPseudoInsts.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVFrameLowering.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVFrameLowering.h
[Alignment][NFC] Use Align for TargetFrameLowering/Subtarget
2019-10-17 07:49:39 +00:00
RISCVInstrFormats.td
…
RISCVInstrFormatsC.td
…
RISCVInstrInfo.cpp
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
2019-11-05 09:39:06 +00:00
RISCVInstrInfo.h
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
2019-11-05 09:39:06 +00:00
RISCVInstrInfo.td
[RISCV] Lower llvm.trap and llvm.debugtrap
2019-10-28 09:54:33 +00:00
RISCVInstrInfoA.td
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
RISCVInstrInfoC.td
[RISCV] Added missing ImmLeaf predicates
2019-10-04 23:42:07 +00:00
RISCVInstrInfoD.td
…
RISCVInstrInfoF.td
[RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)
2019-10-03 15:47:28 +00:00
RISCVInstrInfoM.td
…
RISCVInstructionSelector.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Fix static analysis issues
2019-09-20 13:48:02 +00:00
RISCVISelLowering.cpp
[RISCV] Implement the TargetLowering::getRegisterByName hook
2019-11-04 11:23:54 +00:00
RISCVISelLowering.h
[RISCV] Implement the TargetLowering::getRegisterByName hook
2019-11-04 11:23:54 +00:00
RISCVLegalizerInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Delete a ctor that is commented out. NFC
2019-07-05 08:25:14 +00:00
RISCVMCInstLower.cpp
[RISCV] Add lowering of global TLS addresses
2019-06-19 08:40:59 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp
[RISCV] Remove RA from reserved register to use as callee saved register
2019-10-29 11:32:16 +08:00
RISCVRegisterInfo.h
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVRegisterInfo.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVSubtarget.cpp
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVSubtarget.h
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
RISCVSystemOperands.td
[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVTargetMachine.h
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64
2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00