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clang-p2996/llvm/test/CodeGen/MIR/X86
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Amy Huang a078c77d72 [MIR] Add MIR parsing for heap alloc site instruction markers 
Summary:
This patch adds MIR parsing and printing for heap alloc markers, which were
added in D69136. They are printed as an operand similar to pre-/post-instr
symbols, with a heap-alloc-marker token and a metadata node.

Reviewers: rnk

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69864
2019-11-05 12:57:45 -08:00
..
auto-successor.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
basic-block-liveins.mir
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basic-block-not-at-start-of-line-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
block-address-operands.mir
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branch-folder-with-debug.mir
[BranchFolding] skip debug instr to avoid code change
2019-10-29 11:45:38 +00:00
branch-folder-with-label.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
branch-probabilities.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
call-site-info-error1.mir
[MachineFunction] Base support for call site info tracking
2019-06-27 07:48:06 +00:00
call-site-info-error2.mir
Add a missing space in a MIR parser error message
2019-09-20 14:41:41 +00:00
call-site-info-error3.mir
[MachineFunction] Base support for call site info tracking
2019-06-27 07:48:06 +00:00
call-site-info-error4.mir
[MachineFunction] Base support for call site info tracking
2019-06-27 07:48:06 +00:00
callee-saved-info.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-def-cfa-offset.mir
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cfi-def-cfa-register.mir
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cfi-offset.mir
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constant-pool-item-redefinition-error.mir
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constant-pool.mir
[X86] Model MXCSR for all SSE instructions
2019-10-30 15:07:49 -07:00
constant-value-error.mir
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copyIRflags.mir
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dead-register-flag.mir
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def-register-already-tied-error.mir
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diexpr-win32.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
duplicate-memory-operand-flag.mir
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duplicate-register-flag-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
early-clobber-register-flag.mir
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empty0.mir
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empty1.mir
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empty2.mir
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escape-function-name.ll
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expected-align-in-memory-operand.mir
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expected-alignment-after-align-in-memory-operand.mir
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expected-basic-block-at-start-of-body.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-block-reference-in-blockaddress.mir
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expected-comma-after-cfi-register.mir
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expected-comma-after-memory-operand.mir
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expected-different-implicit-operand.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-different-implicit-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-function-reference-after-blockaddress.mir
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expected-global-value-after-blockaddress.mir
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expected-integer-after-offset-sign.mir
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expected-integer-after-tied-def.mir
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expected-integer-in-successor-weight.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-load-or-store-in-memory-operand.mir
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expected-machine-operand.mir
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expected-metadata-node-after-debug-location.mir
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expected-metadata-node-after-exclaim.mir
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expected-metadata-node-in-stack-object.mir
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expected-named-register-in-allocation-hint.mir
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expected-named-register-in-callee-saved-register.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-named-register-in-functions-livein.mir
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expected-named-register-livein.mir
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expected-newline-at-end-of-list.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-number-after-bb.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-offset-after-cfi-operand.mir
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expected-pointer-value-in-memory-operand.mir
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expected-positive-alignment-after-align.mir
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expected-power-of-2-after-align.mir
MIR: Reject non-power-of-4 alignments in MMO parsing
2019-01-30 23:09:28 +00:00
expected-register-after-cfi-operand.mir
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expected-register-after-flags.mir
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expected-size-integer-after-memory-operation2.mir
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expected-size-integer-after-memory-operation.mir
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expected-stack-object.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
expected-subregister-after-colon.mir
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expected-target-flag-name.mir
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expected-tied-def-after-lparen.mir
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expected-value-in-memory-operand.mir
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expected-virtual-register-in-functions-livein.mir
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external-symbol-operands.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
fastmath.mir
[X86] Model MXCSR for all SSE instructions
2019-10-30 15:07:49 -07:00
fixed-stack-di.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
fixed-stack-memory-operands.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
fixed-stack-object-redefinition-error.mir
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fixed-stack-objects.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
frame-info-save-restore-points.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
frame-info-stack-references.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
frame-setup-instruction-flag.mir
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function-liveins.mir
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generic-instr-type.mir
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global-value-operands.mir
Print quoted backslashes in LLVM IR as \\ instead of \5C
2019-10-10 18:31:57 +00:00
immediate-operands.mir
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implicit-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
inline-asm-registers.mir
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inline-asm.mir
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instr-heap-alloc-operands.mir
[MIR] Add MIR parsing for heap alloc site instruction markers
2019-11-05 12:57:45 -08:00
instr-symbols-and-mcsymbol-operands.mir
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instructions-debug-location.mir
[mir] Serialize DILocation inline when not possible to use a metadata reference
2018-12-13 14:25:27 +00:00
invalid-constant-pool-item.mir
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invalid-debug-location.mir
MIRParser: Check that instructions only reference DILocation metadata
2018-10-01 17:50:52 +00:00
invalid-metadata-node-type.mir
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invalid-target-flag-name.mir
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invalid-tied-def-index-error.mir
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jump-table-info.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
jump-table-redefinition-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
killed-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
large-cfi-offset-number-error.mir
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large-immediate-operand-error.mir
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large-index-number-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
large-offset-number-error.mir
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large-size-in-memory-operand-error.mir
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lit.local.cfg
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liveout-register-mask.mir
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machine-basic-block-operands.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
machine-instructions.mir
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machine-verifier.mir
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memory-operands.mir
[X86] Model MXCSR for all SSE instructions
2019-10-30 15:07:49 -07:00
metadata-operands.mir
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missing-closing-quote.mir
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missing-comma.mir
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missing-implicit-operand.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
named-registers.mir
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newline-handling.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
null-register-operands.mir
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pr38773.mir
[DebugInfo] MCP: collect and update DBG_VALUEs encountered in local block
2019-08-14 12:20:02 +00:00
register-mask-operands.mir
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register-operand-class-invalid0.mir
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register-operand-class-invalid1.mir
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register-operand-class.mir
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register-operands-target-flag-error.mir
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renamable-register-flag.mir
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roundtrip.mir
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simple-register-allocation-hints.mir
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spill-slot-fixed-stack-object-aliased.mir
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spill-slot-fixed-stack-object-immutable.mir
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spill-slot-fixed-stack-objects.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
stack-object-debug-info.mir
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stack-object-invalid-name.mir
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stack-object-operand-name-mismatch-error.mir
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stack-object-operands.mir
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stack-object-redefinition-error.mir
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stack-objects.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
standalone-register-error.mir
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subreg-on-physreg.mir
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subregister-index-operands.mir
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subregister-operands.mir
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successor-basic-blocks-weights.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
successor-basic-blocks.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
tied-def-operand-invalid.mir
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tied-physical-regs-match.mir
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undef-register-flag.mir
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undefined-fixed-stack-object.mir
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undefined-global-value.mir
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undefined-ir-block-in-blockaddress.mir
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undefined-ir-block-slot-in-blockaddress.mir
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undefined-jump-table-id.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
undefined-named-global-value.mir
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undefined-register-class.mir
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undefined-stack-object.mir
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undefined-value-in-memory-operand.mir
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undefined-virtual-register.mir
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unexpected-type-phys.mir
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unknown-instruction.mir
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unknown-machine-basic-block.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
unknown-metadata-keyword.mir
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unknown-metadata-node.mir
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unknown-named-machine-basic-block.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
unknown-register.mir
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unknown-subregister-index-op.mir
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unknown-subregister-index.mir
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unreachable_block.ll
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unrecognized-character.mir
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variable-sized-stack-object-size-error.mir
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variable-sized-stack-objects.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
virtual-register-redefinition-error.mir
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virtual-registers.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
zero-probability.mir
Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir
2018-11-07 23:33:55 +00:00