Stanislav Mekhanoshin 6071e1aa58 [AMDGPU] Simplify negated condition ...

Optimize sequence:

  %sel = V_CNDMASK_B32_e64 0, 1, %cc
  %cmp = V_CMP_NE_U32 1, %1
  $vcc = S_AND_B64 $exec, %cmp
  S_CBRANCH_VCC[N]Z
=>
  $vcc = S_ANDN2_B64 $exec, %cc
  S_CBRANCH_VCC[N]Z

It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
rebuildSetCC().

Differential Revision: https://reviews.llvm.org/D55402

llvm-svn: 349003

2018-12-13 03:17:40 +00:00

..

AArch64

Revert r348843 "[CodeGen] Allow mempcy/memset to generate small overlapping stores."

2018-12-11 13:38:43 +00:00

AMDGPU

[AMDGPU] Simplify negated condition

2018-12-13 03:17:40 +00:00

ARC

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ARM

[ARM GlobalISel] Select load/store for Thumb2

2018-12-12 10:32:15 +00:00

AVR

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BPF

…

Generic

Move llc-start-stop-instance to x86

2018-12-04 18:19:08 +00:00

Hexagon

[Hexagon] Couple of fixes in optimize addressing mode

2018-12-10 21:56:04 +00:00

Inputs

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Lanai

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

Mips

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MIR

[CodeGen] Fix bugs in BranchFolderPass when debug labels are generated.

2018-11-30 08:07:29 +00:00

MSP430

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Nios2

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NVPTX

[NVPTX] do not rely on cached subtarget info.

2018-12-12 18:31:04 +00:00

PowerPC

Revert r348843 "[CodeGen] Allow mempcy/memset to generate small overlapping stores."

2018-12-11 13:38:43 +00:00

RISCV

[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases

2018-12-01 05:00:00 +00:00

SPARC

[Targets] Fixup incorrect targets in codemodel tests

2018-12-10 20:55:34 +00:00

SystemZ

[TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts

2018-12-12 13:43:07 +00:00

Thumb

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Thumb2

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WebAssembly

[WebAssembly] Add '.eventtype' directive support

2018-12-11 01:11:04 +00:00

WinCFGuard

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WinEH

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X86

[X86] Don't emit MULX by default with BMI2

2018-12-12 21:21:31 +00:00

XCore

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00