2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
375 lines
10 KiB
C++
375 lines
10 KiB
C++
//===-- ARMUtils.h ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_ARMUtils_h_
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#define lldb_ARMUtils_h_
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#include "ARMDefines.h"
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#include "InstructionUtils.h"
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#include "llvm/Support/MathExtras.h"
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// Common utilities for the ARM/Thumb Instruction Set Architecture.
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namespace lldb_private {
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static inline uint32_t Align(uint32_t val, uint32_t alignment) {
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return alignment * (val / alignment);
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}
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static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5,
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ARM_ShifterType &shift_t) {
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switch (type) {
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default:
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// assert(0 && "Invalid shift type");
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case 0:
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shift_t = SRType_LSL;
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return imm5;
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case 1:
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shift_t = SRType_LSR;
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return (imm5 == 0 ? 32 : imm5);
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case 2:
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shift_t = SRType_ASR;
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return (imm5 == 0 ? 32 : imm5);
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case 3:
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if (imm5 == 0) {
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shift_t = SRType_RRX;
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return 1;
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} else {
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shift_t = SRType_ROR;
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return imm5;
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}
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}
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shift_t = SRType_Invalid;
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return UINT32_MAX;
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}
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// A8.6.35 CMP (register) -- Encoding T3
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// Convenience function.
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static inline uint32_t DecodeImmShiftThumb(const uint32_t opcode,
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ARM_ShifterType &shift_t) {
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return DecodeImmShift(Bits32(opcode, 5, 4),
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Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6),
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shift_t);
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}
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// A8.6.35 CMP (register) -- Encoding A1
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// Convenience function.
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static inline uint32_t DecodeImmShiftARM(const uint32_t opcode,
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ARM_ShifterType &shift_t) {
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return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t);
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}
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static inline uint32_t DecodeImmShift(const ARM_ShifterType shift_t,
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const uint32_t imm5) {
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ARM_ShifterType dont_care;
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return DecodeImmShift(shift_t, imm5, dont_care);
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}
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static inline ARM_ShifterType DecodeRegShift(const uint32_t type) {
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switch (type) {
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default:
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// assert(0 && "Invalid shift type");
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return SRType_Invalid;
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case 0:
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return SRType_LSL;
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case 1:
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return SRType_LSR;
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case 2:
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return SRType_ASR;
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case 3:
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return SRType_ROR;
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}
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}
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static inline uint32_t LSL_C(const uint32_t value, const uint32_t amount,
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uint32_t &carry_out, bool *success) {
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if (amount == 0) {
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*success = false;
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return 0;
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}
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*success = true;
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carry_out = amount <= 32 ? Bit32(value, 32 - amount) : 0;
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return value << amount;
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}
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static inline uint32_t LSL(const uint32_t value, const uint32_t amount,
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bool *success) {
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*success = true;
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if (amount == 0)
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return value;
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uint32_t dont_care;
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uint32_t result = LSL_C(value, amount, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t LSR_C(const uint32_t value, const uint32_t amount,
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uint32_t &carry_out, bool *success) {
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if (amount == 0) {
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*success = false;
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return 0;
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}
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*success = true;
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carry_out = amount <= 32 ? Bit32(value, amount - 1) : 0;
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return value >> amount;
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}
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static inline uint32_t LSR(const uint32_t value, const uint32_t amount,
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bool *success) {
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*success = true;
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if (amount == 0)
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return value;
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uint32_t dont_care;
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uint32_t result = LSR_C(value, amount, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t ASR_C(const uint32_t value, const uint32_t amount,
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uint32_t &carry_out, bool *success) {
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if (amount == 0 || amount > 32) {
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*success = false;
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return 0;
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}
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*success = true;
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bool negative = BitIsSet(value, 31);
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if (amount <= 32) {
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carry_out = Bit32(value, amount - 1);
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int64_t extended = llvm::SignExtend64<32>(value);
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return UnsignedBits(extended, amount + 31, amount);
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} else {
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carry_out = (negative ? 1 : 0);
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return (negative ? 0xffffffff : 0);
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}
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}
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static inline uint32_t ASR(const uint32_t value, const uint32_t amount,
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bool *success) {
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*success = true;
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if (amount == 0)
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return value;
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uint32_t dont_care;
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uint32_t result = ASR_C(value, amount, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t ROR_C(const uint32_t value, const uint32_t amount,
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uint32_t &carry_out, bool *success) {
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if (amount == 0) {
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*success = false;
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return 0;
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}
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*success = true;
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uint32_t amt = amount % 32;
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uint32_t result = Rotr32(value, amt);
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carry_out = Bit32(value, 31);
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return result;
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}
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static inline uint32_t ROR(const uint32_t value, const uint32_t amount,
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bool *success) {
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*success = true;
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if (amount == 0)
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return value;
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uint32_t dont_care;
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uint32_t result = ROR_C(value, amount, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t RRX_C(const uint32_t value, const uint32_t carry_in,
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uint32_t &carry_out, bool *success) {
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*success = true;
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carry_out = Bit32(value, 0);
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return Bit32(carry_in, 0) << 31 | Bits32(value, 31, 1);
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}
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static inline uint32_t RRX(const uint32_t value, const uint32_t carry_in,
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bool *success) {
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*success = true;
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uint32_t dont_care;
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uint32_t result = RRX_C(value, carry_in, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t Shift_C(const uint32_t value, ARM_ShifterType type,
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const uint32_t amount, const uint32_t carry_in,
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uint32_t &carry_out, bool *success) {
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if (type == SRType_RRX && amount != 1) {
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*success = false;
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return 0;
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}
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*success = true;
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if (amount == 0) {
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carry_out = carry_in;
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return value;
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}
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uint32_t result;
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switch (type) {
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case SRType_LSL:
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result = LSL_C(value, amount, carry_out, success);
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break;
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case SRType_LSR:
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result = LSR_C(value, amount, carry_out, success);
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break;
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case SRType_ASR:
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result = ASR_C(value, amount, carry_out, success);
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break;
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case SRType_ROR:
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result = ROR_C(value, amount, carry_out, success);
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break;
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case SRType_RRX:
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result = RRX_C(value, carry_in, carry_out, success);
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break;
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default:
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*success = false;
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break;
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}
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t Shift(const uint32_t value, ARM_ShifterType type,
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const uint32_t amount, const uint32_t carry_in,
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bool *success) {
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// Don't care about carry out in this case.
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uint32_t dont_care;
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uint32_t result = Shift_C(value, type, amount, carry_in, dont_care, success);
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if (*success)
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return result;
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else
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return 0;
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}
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static inline uint32_t bits(const uint32_t val, const uint32_t msbit,
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const uint32_t lsbit) {
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return Bits32(val, msbit, lsbit);
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}
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static inline uint32_t bit(const uint32_t val, const uint32_t msbit) {
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return bits(val, msbit, msbit);
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}
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static uint32_t ror(uint32_t val, uint32_t N, uint32_t shift) {
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uint32_t m = shift % N;
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return (val >> m) | (val << (N - m));
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}
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// (imm32, carry_out) = ARMExpandImm_C(imm12, carry_in)
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static inline uint32_t ARMExpandImm_C(uint32_t opcode, uint32_t carry_in,
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uint32_t &carry_out) {
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uint32_t imm32; // the expanded result
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uint32_t imm = bits(opcode, 7, 0); // immediate value
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uint32_t amt = 2 * bits(opcode, 11, 8); // rotate amount
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if (amt == 0) {
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imm32 = imm;
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carry_out = carry_in;
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} else {
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imm32 = ror(imm, 32, amt);
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carry_out = Bit32(imm32, 31);
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}
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return imm32;
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}
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static inline uint32_t ARMExpandImm(uint32_t opcode) {
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// 'carry_in' argument to following function call does not affect the imm32
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// result.
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uint32_t carry_in = 0;
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uint32_t carry_out;
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return ARMExpandImm_C(opcode, carry_in, carry_out);
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}
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// (imm32, carry_out) = ThumbExpandImm_C(imm12, carry_in)
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static inline uint32_t ThumbExpandImm_C(uint32_t opcode, uint32_t carry_in,
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uint32_t &carry_out) {
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uint32_t imm32; // the expanded result
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const uint32_t i = bit(opcode, 26);
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const uint32_t imm3 = bits(opcode, 14, 12);
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const uint32_t abcdefgh = bits(opcode, 7, 0);
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const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh;
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if (bits(imm12, 11, 10) == 0) {
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switch (bits(imm12, 9, 8)) {
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default: // Keep static analyzer happy with a default case
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case 0:
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imm32 = abcdefgh;
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break;
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case 1:
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imm32 = abcdefgh << 16 | abcdefgh;
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break;
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case 2:
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imm32 = abcdefgh << 24 | abcdefgh << 8;
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break;
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case 3:
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imm32 = abcdefgh << 24 | abcdefgh << 16 | abcdefgh << 8 | abcdefgh;
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break;
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}
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carry_out = carry_in;
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} else {
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const uint32_t unrotated_value = 0x80 | bits(imm12, 6, 0);
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imm32 = ror(unrotated_value, 32, bits(imm12, 11, 7));
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carry_out = Bit32(imm32, 31);
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}
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return imm32;
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}
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static inline uint32_t ThumbExpandImm(uint32_t opcode) {
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// 'carry_in' argument to following function call does not affect the imm32
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// result.
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uint32_t carry_in = 0;
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uint32_t carry_out;
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return ThumbExpandImm_C(opcode, carry_in, carry_out);
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}
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// imm32 = ZeroExtend(i:imm3:imm8, 32)
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static inline uint32_t ThumbImm12(uint32_t opcode) {
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const uint32_t i = bit(opcode, 26);
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const uint32_t imm3 = bits(opcode, 14, 12);
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const uint32_t imm8 = bits(opcode, 7, 0);
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const uint32_t imm12 = i << 11 | imm3 << 8 | imm8;
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return imm12;
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}
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// imm32 = ZeroExtend(imm7:'00', 32)
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static inline uint32_t ThumbImm7Scaled(uint32_t opcode) {
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const uint32_t imm7 = bits(opcode, 6, 0);
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return imm7 * 4;
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}
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// imm32 = ZeroExtend(imm8:'00', 32)
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static inline uint32_t ThumbImm8Scaled(uint32_t opcode) {
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const uint32_t imm8 = bits(opcode, 7, 0);
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return imm8 * 4;
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}
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// This function performs the check for the register numbers 13 and 15 that are
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// not permitted for many Thumb register specifiers.
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static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; }
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} // namespace lldb_private
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#endif // lldb_ARMUtils_h_
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