a45f301f7a
It caused assertions to fire when building Chromium:
lib/CodeGen/LiveDebugValues.cpp:331: bool
{anonymous}::LiveDebugValues::OpenRangesSet::empty() const: Assertion
`Vars.empty() == VarLocs.empty() && "open ranges are inconsistent"' failed.
See https://crbug.com/992871#c3 for how to reproduce.
> Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.
>
> To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.
>
> Differential Revision: https://reviews.llvm.org/D65673
llvm-svn: 368579
161 lines
5.6 KiB
LLVM
161 lines
5.6 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; OPT-LABEL: {{^}}define amdgpu_vs void @multi_else_break(
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; OPT: main_body:
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; OPT: LOOP.outer:
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; OPT: LOOP:
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; OPT: [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if.i64(
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; OPT: [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1
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;
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; OPT: Flow:
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;
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; Ensure two if.break calls, for both the inner and outer loops
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; OPT: call void @llvm.amdgcn.end.cf
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; OPT-NEXT: call i64 @llvm.amdgcn.if.break.i64.i64(i1
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; OPT-NEXT: call i1 @llvm.amdgcn.loop.i64(i64
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; OPT-NEXT: call i64 @llvm.amdgcn.if.break.i64.i64(i1
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;
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; OPT: Flow1:
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; GCN-LABEL: {{^}}multi_else_break:
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; GCN: ; %main_body
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; GCN: s_mov_b64 [[LEFT_OUTER:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: [[FLOW2:BB[0-9]+_[0-9]+]]: ; %Flow2
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; GCN: s_or_b64 exec, exec, [[TMP0:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK_OUTER:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 [[TMP1]], [[TMP1]], [[LEFT_OUTER]]
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; GCN: s_mov_b64 [[LEFT_OUTER]], [[TMP1]]
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; GCN: s_andn2_b64 exec, exec, [[TMP1]]
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; GCN: s_cbranch_execz [[IF_BLOCK:BB[0-9]+_[0-9]+]]
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; GCN: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP.outer{{$}}
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; GCN: s_mov_b64 [[LEFT_INNER:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: ; %Flow
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; GCN: s_or_b64 exec, exec, [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 [[TMP0]], exec, [[BREAK_INNER:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 [[TMP0]], [[TMP0]], [[LEFT_INNER]]
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; GCN: s_mov_b64 [[LEFT_INNER]], [[TMP0]]
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; GCN: s_andn2_b64 exec, exec, [[TMP0]]
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; GCN: s_cbranch_execz [[FLOW2]]
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; GCN: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP{{$}}
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; GCN: s_or_b64 [[BREAK_OUTER]], [[BREAK_OUTER]], exec
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; GCN: s_or_b64 [[BREAK_INNER]], [[BREAK_INNER]], exec
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; GCN: s_and_saveexec_b64 [[SAVE_EXEC]], vcc
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; FIXME: duplicate comparison
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; GCN: ; %ENDIF
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; GCN-DAG: v_cmp_eq_u32_e32 vcc,
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; GCN-DAG: v_cmp_ne_u32_e64 [[TMP51NEG:s\[[0-9]+:[0-9]+\]]],
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; GCN-DAG: s_andn2_b64 [[BREAK_OUTER]], [[BREAK_OUTER]], exec
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; GCN-DAG: s_andn2_b64 [[BREAK_INNER]], [[BREAK_INNER]], exec
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; GCN-DAG: s_and_b64 [[TMP_EQ:s\[[0-9]+:[0-9]+\]]], vcc, exec
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; GCN-DAG: s_and_b64 [[TMP_NE:s\[[0-9]+:[0-9]+\]]], [[TMP51NEG]], exec
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; GCN-DAG: s_or_b64 [[BREAK_OUTER]], [[BREAK_OUTER]], [[TMP_EQ]]
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; GCN-DAG: s_or_b64 [[BREAK_INNER]], [[BREAK_INNER]], [[TMP_NE]]
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; GCN: [[IF_BLOCK]]: ; %IF
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; GCN-NEXT: s_endpgm
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define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
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main_body:
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br label %LOOP.outer
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LOOP.outer: ; preds = %ENDIF, %main_body
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%tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
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br label %LOOP
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LOOP: ; preds = %ENDIF, %LOOP.outer
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%tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
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%tmp47 = add i32 %tmp45, 1
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%tmp48 = icmp slt i32 %tmp45, %ub
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br i1 %tmp48, label %ENDIF, label %IF
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IF: ; preds = %LOOP
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ret void
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ENDIF: ; preds = %LOOP
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%tmp51 = icmp eq i32 %tmp47, %cont
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br i1 %tmp51, label %LOOP, label %LOOP.outer
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}
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; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.loop
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.end.cf
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; GCN-LABEL: {{^}}multi_if_break_loop:
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; GCN: s_mov_b64 [[LEFT:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: ; %Flow4
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; GCN: s_and_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[BREAK]]
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; GCN: s_or_b64 [[LEFT]], [[BREAK]], [[OLD_LEFT:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_andn2_b64 exec, exec, [[LEFT]]
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; GCN-NEXT: s_cbranch_execz
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; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; %bb1{{$}}
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; GCN: s_mov_b64 [[OLD_LEFT]], [[LEFT]]
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; GCN: ; %LeafBlock1
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; GCN: s_mov_b64
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; GCN: s_mov_b64 [[BREAK]], -1{{$}}
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; GCN: ; %case1
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; GCN: buffer_load_dword [[LOAD2:v[0-9]+]],
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; GCN: v_cmp_ge_i32_e32 vcc, {{v[0-9]+}}, [[LOAD2]]
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; GCN: s_orn2_b64 [[BREAK]], vcc, exec
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; GCN: ; %Flow3
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; GCN: s_branch [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: s_mov_b64 [[BREAK]], -1{{$}}
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; GCN: [[FLOW]]: ; %Flow
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; GCN: ; %case0
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; GCN: buffer_load_dword [[LOAD1:v[0-9]+]],
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; GCN-DAG: s_andn2_b64 [[BREAK]], [[BREAK]], exec
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; GCN-DAG: v_cmp_ge_i32_e32 vcc, {{v[0-9]+}}, [[LOAD1]]
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; GCN-DAG: s_and_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], vcc, exec
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; GCN: s_or_b64 [[BREAK]], [[BREAK]], [[TMP]]
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define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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%load0 = load volatile i32, i32 addrspace(1)* undef, align 4
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switch i32 %load0, label %bb9 [
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i32 0, label %case0
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i32 1, label %case1
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]
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case0:
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%load1 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load1
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br i1 %cmp1, label %bb1, label %bb9
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case1:
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%load2 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp2 = icmp slt i32 %tmp, %load2
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br i1 %cmp2, label %bb1, label %bb9
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bb9:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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