60a446ab02
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
252 lines
8.5 KiB
C++
252 lines
8.5 KiB
C++
//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// CodeEmitterGen uses the descriptions of instructions and their fields to
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// construct an automated code emitter: a function that, given a MachineInstr,
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// returns the (currently, 32-bit unsigned) value of the instruction.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeEmitterGen.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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if (R->getName() == "PHI" ||
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R->getName() == "INLINEASM" ||
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R->getName() == "DBG_LABEL" ||
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R->getName() == "EH_LABEL" ||
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R->getName() == "GC_LABEL" ||
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R->getName() == "DECLARE" ||
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R->getName() == "EXTRACT_SUBREG" ||
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "COPY_TO_SUBCLASS") continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned numBits = BI->getNumBits();
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BitsInit *NewBI = new BitsInit(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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Init *OrigBit = BI->getBit(bit);
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Init *BitSwap = BI->getBit(bitSwapIdx);
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NewBI->setBit(bit, BitSwap);
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NewBI->setBit(bitSwapIdx, OrigBit);
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}
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if (numBits % 2) {
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unsigned middle = (numBits + 1) / 2;
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NewBI->setBit(middle, BI->getBit(middle));
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}
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// Update the bits in reversed order so that emitInstrOpBits will get the
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// correct endianness.
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R->getValue("Inst")->setValue(NewBI);
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}
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}
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// If the VarBitInit at position 'bit' matches the specified variable then
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// return the variable bit position. Otherwise return -1.
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int CodeEmitterGen::getVariableBit(const std::string &VarName,
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BitsInit *BI, int bit) {
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if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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if (VI->getName() == VarName) return VBI->getBitNum();
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}
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}
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return -1;
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}
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void CodeEmitterGen::run(std::ostream &o) {
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CodeGenTarget Target;
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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// For little-endian instruction bit encodings, reverse the bit order
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if (Target.isLittleEndianEncoding()) reverseBits(Insts);
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EmitSourceFileHeader("Machine Code Emitter", o);
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std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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// Emit function declaration
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o << "unsigned " << Target.getName() << "CodeEmitter::"
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<< "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
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// Emit instruction base values
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o << " static const unsigned InstBits[] = {\n";
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for (std::vector<const CodeGenInstruction*>::iterator
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IN = NumberedInstructions.begin(),
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EN = NumberedInstructions.end();
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IN != EN; ++IN) {
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const CodeGenInstruction *CGI = *IN;
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Record *R = CGI->TheDef;
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if (R->getName() == "PHI" ||
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R->getName() == "INLINEASM" ||
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R->getName() == "DBG_LABEL" ||
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R->getName() == "EH_LABEL" ||
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R->getName() == "GC_LABEL" ||
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R->getName() == "DECLARE" ||
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R->getName() == "EXTRACT_SUBREG" ||
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "COPY_TO_SUBCLASS") {
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o << " 0U,\n";
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continue;
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}
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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// Start by filling in fixed values...
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unsigned Value = 0;
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
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Value |= B->getValue() << (e-i-1);
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}
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}
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o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n";
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}
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o << " 0U\n };\n";
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// Map to accumulate all the cases.
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std::map<std::string, std::vector<std::string> > CaseMap;
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// Construct all cases statement for each opcode
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for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
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IC != EC; ++IC) {
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Record *R = *IC;
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const std::string &InstName = R->getName();
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std::string Case("");
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if (InstName == "PHI" ||
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InstName == "INLINEASM" ||
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InstName == "DBG_LABEL"||
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InstName == "EH_LABEL"||
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InstName == "GC_LABEL"||
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InstName == "DECLARE"||
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InstName == "EXTRACT_SUBREG" ||
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InstName == "INSERT_SUBREG" ||
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InstName == "IMPLICIT_DEF" ||
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InstName == "SUBREG_TO_REG" ||
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InstName == "COPY_TO_SUBCLASS") continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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const std::vector<RecordVal> &Vals = R->getValues();
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CodeGenInstruction &CGI = Target.getInstruction(InstName);
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// Loop over all of the fields in the instruction, determining which are the
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// operands to the instruction.
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unsigned op = 0;
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for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
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if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
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// Is the operand continuous? If so, we can just mask and OR it in
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// instead of doing it bit-by-bit, saving a lot in runtime cost.
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const std::string &VarName = Vals[i].getName();
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bool gotOp = false;
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for (int bit = BI->getNumBits()-1; bit >= 0; ) {
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int varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1) {
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--bit;
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} else {
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int beginInstBit = bit;
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int beginVarBit = varBit;
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int N = 1;
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for (--bit; bit >= 0;) {
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varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1 || varBit != (beginVarBit - N)) break;
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++N;
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--bit;
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}
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if (!gotOp) {
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/// If this operand is not supposed to be emitted by the generated
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/// emitter, skip it.
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while (CGI.isFlatOperandNotEmitted(op))
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++op;
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Case += " // op: " + VarName + "\n"
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+ " op = getMachineOpValue(MI, MI.getOperand("
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+ utostr(op++) + "));\n";
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gotOp = true;
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}
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unsigned opMask = ~0U >> (32-N);
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int opShift = beginVarBit - N + 1;
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opMask <<= opShift;
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opShift = beginInstBit - beginVarBit;
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if (opShift > 0) {
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Case += " Value |= (op & " + utostr(opMask) + "U) << "
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+ itostr(opShift) + ";\n";
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} else if (opShift < 0) {
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Case += " Value |= (op & " + utostr(opMask) + "U) >> "
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+ itostr(-opShift) + ";\n";
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} else {
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Case += " Value |= op & " + utostr(opMask) + "U;\n";
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}
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}
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}
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}
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}
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std::vector<std::string> &InstList = CaseMap[Case];
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InstList.push_back(InstName);
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}
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// Emit initial function code
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o << " const unsigned opcode = MI.getOpcode();\n"
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<< " unsigned Value = InstBits[opcode];\n"
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<< " unsigned op = 0;\n"
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<< " op = op; // suppress warning\n"
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<< " switch (opcode) {\n";
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// Emit each case statement
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std::map<std::string, std::vector<std::string> >::iterator IE, EE;
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for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
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const std::string &Case = IE->first;
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std::vector<std::string> &InstList = IE->second;
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for (int i = 0, N = InstList.size(); i < N; i++) {
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if (i) o << "\n";
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o << " case " << Namespace << InstList[i] << ":";
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}
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o << " {\n";
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o << Case;
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o << " break;\n"
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<< " }\n";
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}
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// Default case: unhandled opcode
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o << " default:\n"
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<< " cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
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<< " abort();\n"
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<< " }\n"
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<< " return Value;\n"
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<< "}\n\n";
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}
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