Matt Arsenault ff07631b48 AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization ...

llvm-svn: 370089

2019-08-27 18:18:38 +00:00

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expected-target-index-name.mir

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intrinsics.mir

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invalid-target-index-operand.mir

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lit.local.cfg

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load-store-opt-dlc.mir

AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructions

2019-07-29 16:40:58 +00:00

machine-function-info-no-ir.mir

AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization

2019-08-27 18:18:38 +00:00

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization

2019-08-27 18:18:38 +00:00

mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-scratch-wave-offset-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-scratch-wave-offset-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

[MIR-Canon] Hardening propagateLocalCopies.

2019-05-31 04:49:58 +00:00

parse-order-reserved-regs.mir

[MIR-Canon] Don't do vreg skip for independent instructions if there are none.

2019-05-31 17:34:25 +00:00

stack-id.mir

Describe stack-id as an enum

2019-06-17 09:13:29 +00:00

syncscopes.mir

[AMDGPU] gfx1010 VMEM and SMEM implementation

2019-04-30 22:08:23 +00:00

target-flags.mir

AMDGPU: Prepare for explicit absolute relocations in code generation

2019-06-16 17:43:37 +00:00

target-index-operands.mir

[AMDGPU] gfx1010 VMEM and SMEM implementation

2019-04-30 22:08:23 +00:00