6206f5444f
Occupancy (i.e., the number of waves per EU) depends, in addition to register usage, on per-workgroup LDS usage as well as on the range of possible workgroup sizes. Mirroring the latter, occupancy should therefore be expressed as a range since different group sizes generally yield different achievable occupancies. `getOccupancyWithLocalMemSize` currently returns a scalar occupancy based on the maximum workgroup size and LDS usage. With respect to the workgroup size range, this scalar can be the minimum, the maximum, or neither of the two of the range of achievable occupancies. This commit fixes the function by making it compute and return the range of achievable occupancies w.r.t. workgroup size and LDS usage; it also renames it to `getOccupancyWithWorkGroupSizes` since it is the range of workgroup sizes that produces the range of achievable occupancies. Computing the achievable occupancy range is surprisingly involved. Minimum/maximum workgroup sizes do not necessarily yield maximum/minimum occupancies i.e., sometimes workgroup sizes inside the range yield the occupancy bounds. The implementation finds these sizes in constant time; heavy documentation explains the rationale behind the sometimes relatively obscure calculations. As a justifying example, consider a target with 10 waves / EU, 4 EUs/CU, 64-wide waves. Also consider a function with no LDS usage and a flat workgroup size range of [513,1024]. - A group of 513 items requires 9 waves per group. Only 4 groups made up of 9 waves each can fit fully on a CU at any given time, for a total of 36 waves on the CU, or 9 per EU. However, filling as much as possible the remaining 40-36=4 wave slots without decreasing the number of groups reveals that a larger group of 640 items yields 40 waves on the CU, or 10 per EU. - Similarly, a group of 1024 items requires 16 waves per group. Only 2 groups made up of 16 waves each can fit fully on a CU ay any given time, for a total of 32 waves on the CU, or 8 per EU. However, removing as many waves as possible from the groups without being able to fit another equal-sized group on the CU reveals that a smaller group of 896 items yields 28 waves on the CU, or 7 per EU. Therefore the achievable occupancy range for this function is not [8,9] as the group size bounds directly yield, but [7,10]. Naturally this change causes a lot of test churn as instruction scheduling is driven by achievable occupancy estimates. In most unit tests the flat workgroup size range is the default [1,1024] which, ignoring potential LDS limitations, would previously produce a scalar occupancy of 8 (derived from 1024) on a lot of targets, whereas we now consider the maximum occupancy to be 10 in such cases. Most tests are updated automatically and checked manually for sanity. I also manually changed some non-automatically generated assertions when necessary. Fixes #118220.
271 lines
11 KiB
LLVM
271 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
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; Make sure that AMDGPUCodeGenPrepare introduces mul24 intrinsics
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; after SLSR, as the intrinsics would interfere. It's unclear if these
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; should be introduced before LSR or not. It seems to help in some
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; cases, and hurt others.
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define void @lsr_order_mul24_0(i32 %arg, i32 %arg2, i32 %arg6, i32 %arg13, i32 %arg16) #0 {
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; GFX9-LABEL: lsr_order_mul24_0:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v5, v[0:1], off
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; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
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; GFX9-NEXT: v_sub_u32_e32 v4, v4, v1
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; GFX9-NEXT: s_mov_b64 s[4:5], 0
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ds_write_b32 v0, v5
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; GFX9-NEXT: .LBB0_1: ; %bb23
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; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX9-NEXT: v_mul_u32_u24_e32 v5, v0, v2
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GFX9-NEXT: v_sub_u32_e32 v5, v4, v5
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; GFX9-NEXT: v_add_u32_e32 v5, v5, v0
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; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
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; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GFX9-NEXT: s_cbranch_execnz .LBB0_1
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; GFX9-NEXT: ; %bb.2: ; %.loopexit
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; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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bb:
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%tmp22 = and i32 %arg6, 16777215
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br label %bb23
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.loopexit: ; preds = %bb23
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ret void
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bb23: ; preds = %bb23, %bb
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%tmp24 = phi i32 [ %arg, %bb ], [ %tmp47, %bb23 ]
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%tmp28 = and i32 %tmp24, 16777215
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%tmp29 = mul i32 %tmp28, %tmp22
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%tmp30 = sub i32 %tmp24, %tmp29
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%tmp31 = add i32 %tmp30, %arg16
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%tmp37 = icmp ult i32 %tmp31, %arg13
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%tmp44 = load float, ptr addrspace(1) undef, align 4
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store float %tmp44, ptr addrspace(3) undef, align 4
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%tmp47 = add i32 %tmp24, %arg2
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br i1 %tmp37, label %bb23, label %.loopexit
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}
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define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(3) nocapture %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, ptr addrspace(1) nocapture readonly %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17, i1 zeroext %arg18) #0 {
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; GFX9-LABEL: lsr_order_mul24_1:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v5, 1, v18
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; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
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; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
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; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
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; GFX9-NEXT: s_cbranch_execz .LBB1_3
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; GFX9-NEXT: ; %bb.1: ; %bb19
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; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
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; GFX9-NEXT: v_add_u32_e32 v4, v4, v0
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; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
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; GFX9-NEXT: v_lshl_add_u32 v6, v4, 2, v3
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; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
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; GFX9-NEXT: v_lshlrev_b32_e32 v8, 2, v2
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; GFX9-NEXT: v_add_u32_e32 v9, v17, v12
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; GFX9-NEXT: s_mov_b64 s[10:11], 0
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; GFX9-NEXT: v_mov_b32_e32 v4, 0
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; GFX9-NEXT: ; implicit-def: $vgpr3
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; GFX9-NEXT: .LBB1_2: ; %bb23
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; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
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; GFX9-NEXT: v_add_u32_e32 v12, v17, v0
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; GFX9-NEXT: v_madak_f32 v3, v3, v7, 0x3727c5ac
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; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
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; GFX9-NEXT: v_mul_u32_u24_e32 v18, v3, v5
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; GFX9-NEXT: v_add_u32_e32 v19, v3, v16
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; GFX9-NEXT: v_add_u32_e32 v3, v9, v0
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; GFX9-NEXT: v_sub_u32_e32 v3, v3, v18
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; GFX9-NEXT: v_sub_u32_e32 v12, v12, v18
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; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v19, v13
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; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v19, v15, v[3:4]
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; GFX9-NEXT: v_cmp_lt_u32_e64 s[6:7], v12, v14
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; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
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; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
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; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, v18, s[4:5]
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; GFX9-NEXT: v_lshlrev_b64 v[18:19], 2, v[3:4]
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
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; GFX9-NEXT: v_add_co_u32_e64 v18, s[6:7], v10, v18
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; GFX9-NEXT: v_addc_co_u32_e64 v19, s[6:7], v11, v19, s[6:7]
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; GFX9-NEXT: global_load_dword v3, v[18:19], off
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; GFX9-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v1
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; GFX9-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5]
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; GFX9-NEXT: ds_write_b32 v6, v3
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; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
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; GFX9-NEXT: s_andn2_b64 exec, exec, s[10:11]
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; GFX9-NEXT: s_cbranch_execnz .LBB1_2
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; GFX9-NEXT: .LBB1_3: ; %Flow2
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; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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bb:
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%tmp = icmp ult i32 %arg, %arg1
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br i1 %tmp, label %bb19, label %.loopexit
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bb19: ; preds = %bb
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%tmp20 = uitofp i32 %arg6 to float
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%tmp21 = fdiv float 1.000000e+00, %tmp20, !fpmath !0
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%tmp22 = and i32 %arg6, 16777215
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br label %bb23
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.loopexit: ; preds = %bb23, %bb
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ret void
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bb23: ; preds = %bb19, %bb23
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%tmp24 = phi i32 [ %arg, %bb19 ], [ %tmp47, %bb23 ]
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%tmp25 = uitofp i32 %tmp24 to float
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%tmp26 = tail call float @llvm.fmuladd.f32(float %tmp25, float %tmp21, float 0x3EE4F8B580000000) #2
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%tmp27 = fptoui float %tmp26 to i32
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%tmp28 = and i32 %tmp27, 16777215
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%tmp29 = mul i32 %tmp28, %tmp22
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%tmp30 = sub i32 %tmp24, %tmp29
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%tmp31 = add i32 %tmp30, %arg16
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%tmp32 = add i32 %tmp27, %arg15
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%tmp33 = mul i32 %tmp32, %arg14
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%tmp34 = add i32 %tmp33, %arg11
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%tmp35 = add i32 %tmp34, %tmp31
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%tmp36 = add i32 %tmp24, %arg4
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%tmp37 = icmp ult i32 %tmp31, %arg13
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%tmp38 = icmp ult i32 %tmp32, %arg12
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%tmp39 = and i1 %tmp38, %tmp37
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%tmp40 = and i1 %tmp39, %arg17
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%tmp41 = zext i32 %tmp35 to i64
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%tmp42 = select i1 %tmp40, i64 %tmp41, i64 0
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%tmp43 = getelementptr inbounds float, ptr addrspace(1) %arg10, i64 %tmp42
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%tmp44 = load float, ptr addrspace(1) %tmp43, align 4
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%tmp45 = select i1 %tmp40, float %tmp44, float 0.000000e+00
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%tmp46 = getelementptr inbounds float, ptr addrspace(3) %arg3, i32 %tmp36
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store float %tmp45, ptr addrspace(3) %tmp46, align 4
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%tmp47 = add i32 %tmp24, %arg2
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%tmp48 = icmp ult i32 %tmp47, %arg1
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br i1 %tmp48, label %bb23, label %.loopexit
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}
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define void @slsr1_0(i32 %b.arg, i32 %s.arg) #0 {
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; GFX9-LABEL: slsr1_0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v1
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; GFX9-NEXT: v_mul_u32_u24_e32 v3, v0, v1
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; GFX9-NEXT: global_store_dword v[0:1], v3, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v2
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%b = and i32 %b.arg, 16777215
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%s = and i32 %s.arg, 16777215
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; CHECK-LABEL: @slsr1(
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; foo(b * s);
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%mul0 = mul i32 %b, %s
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; CHECK: mul i32
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; CHECK-NOT: mul i32
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store volatile i32 %mul0, ptr addrspace(1) undef
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; foo((b + 1) * s);
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%b1 = add i32 %b, 1
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%mul1 = mul i32 %b1, %s
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store volatile i32 %mul1, ptr addrspace(1) undef
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; foo((b + 2) * s);
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%b2 = add i32 %b, 2
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%mul2 = mul i32 %b2, %s
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store volatile i32 %mul2, ptr addrspace(1) undef
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ret void
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}
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define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 {
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; GFX9-LABEL: slsr1_1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s4, s33
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; GFX9-NEXT: s_mov_b32 s33, s32
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; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
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; GFX9-NEXT: s_mov_b64 exec, s[6:7]
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; GFX9-NEXT: v_writelane_b32 v43, s4, 5
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; GFX9-NEXT: v_writelane_b32 v43, s30, 0
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; GFX9-NEXT: v_writelane_b32 v43, s31, 1
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; GFX9-NEXT: s_addk_i32 s32, 0x800
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; GFX9-NEXT: v_writelane_b32 v43, s34, 2
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; GFX9-NEXT: v_writelane_b32 v43, s36, 3
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; GFX9-NEXT: s_getpc_b64 s[4:5]
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; GFX9-NEXT: s_add_u32 s4, s4, foo@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s5, s5, foo@gotpcrel32@hi+12
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; GFX9-NEXT: v_writelane_b32 v43, s37, 4
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; GFX9-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0
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; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
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; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
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; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
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; GFX9-NEXT: v_mov_b32_e32 v40, v1
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; GFX9-NEXT: v_mov_b32_e32 v41, v0
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; GFX9-NEXT: v_mul_u32_u24_e32 v0, v41, v40
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; GFX9-NEXT: s_mov_b32 s34, s15
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; GFX9-NEXT: v_and_b32_e32 v42, 0xffffff, v40
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
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; GFX9-NEXT: v_mad_u32_u24 v40, v41, v40, v42
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; GFX9-NEXT: s_mov_b32 s15, s34
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; GFX9-NEXT: v_mov_b32_e32 v0, v40
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
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; GFX9-NEXT: v_add_u32_e32 v0, v40, v42
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; GFX9-NEXT: s_mov_b32 s15, s34
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
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; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
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; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
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; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
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; GFX9-NEXT: v_readlane_b32 s37, v43, 4
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; GFX9-NEXT: v_readlane_b32 s36, v43, 3
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; GFX9-NEXT: v_readlane_b32 s34, v43, 2
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; GFX9-NEXT: v_readlane_b32 s31, v43, 1
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; GFX9-NEXT: v_readlane_b32 s30, v43, 0
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; GFX9-NEXT: v_readlane_b32 s4, v43, 5
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; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
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; GFX9-NEXT: s_mov_b64 exec, s[6:7]
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; GFX9-NEXT: s_addk_i32 s32, 0xf800
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; GFX9-NEXT: s_mov_b32 s33, s4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%b = and i32 %b.arg, 16777215
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%s = and i32 %s.arg, 16777215
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; CHECK-LABEL: @slsr1(
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; foo(b * s);
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%mul0 = mul i32 %b, %s
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; CHECK: mul i32
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; CHECK-NOT: mul i32
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call void @foo(i32 %mul0)
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; foo((b + 1) * s);
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%b1 = add i32 %b, 1
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%mul1 = mul i32 %b1, %s
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call void @foo(i32 %mul1)
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; foo((b + 2) * s);
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%b2 = add i32 %b, 2
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%mul2 = mul i32 %b2, %s
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call void @foo(i32 %mul2)
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ret void
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}
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declare void @foo(i32) #2
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declare float @llvm.fmuladd.f32(float, float, float) #1
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attributes #0 = { nounwind willreturn "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
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!0 = !{float 2.500000e+00}
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