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clang-p2996/llvm/lib/Target/RISCV
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Evandro Menezes 5d6d8a2769 [RISCV] Add SiFive cores to the CPU option 
Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.

Differential Revision: https://reviews.llvm.org/D88759
2020-10-05 15:50:57 -05:00
..
AsmParser
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
Disassembler
…
MCTargetDesc
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
TargetInfo
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Utils
[RISCV] Support Shadow Call Stack
2020-09-17 16:02:35 -07:00
CMakeLists.txt
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LLVMBuild.txt
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RISCV.h
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RISCV.td
[RISCV] Add SiFive cores to the CPU option
2020-10-05 15:50:57 -05:00
RISCVAsmPrinter.cpp
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RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[RISCV] Support Shadow Call Stack
2020-09-17 16:02:35 -07:00
RISCVFrameLowering.h
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RISCVInstrFormats.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
2020-09-21 10:21:11 +01:00
RISCVInstrInfo.h
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
2020-09-21 10:21:11 +01:00
RISCVInstrInfo.td
[RISCV] Do not mandate scheduling for CSR instructions
2020-09-21 18:24:53 -05:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVInstrInfoC.td
[RISC-V] Mark C_MV as a move instruction
2020-08-27 10:32:23 +01:00
RISCVInstrInfoD.td
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RISCVInstrInfoF.td
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RISCVInstrInfoM.td
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RISCVInstrInfoV.td
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVISelDAGToDAG.h
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVISelLowering.cpp
[RISCV] eliminate the repetition declare of SDLoc DL
2020-08-03 10:24:30 +08:00
RISCVISelLowering.h
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
2020-09-03 20:01:23 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
RISCVSchedBullet.td
[RISCV] Scheduler description for Bullet
2020-09-25 18:36:53 -05:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[X86][MC][Target] Initial backend support a tune CPU to support -mtune
2020-08-14 15:31:50 -07:00
RISCVSubtarget.h
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.
2020-09-09 14:31:12 -07:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00