283b4d6ba3
These mirror the IR and SelectionDAG intrinsics & nodes. Opcodes added: G_VECREDUCE_SEQ_FADD G_VECREDUCE_SEQ_FMUL G_VECREDUCE_FADD G_VECREDUCE_FMUL G_VECREDUCE_FMAX G_VECREDUCE_FMIN G_VECREDUCE_ADD G_VECREDUCE_MUL G_VECREDUCE_AND G_VECREDUCE_OR G_VECREDUCE_XOR G_VECREDUCE_SMAX G_VECREDUCE_SMIN G_VECREDUCE_UMAX G_VECREDUCE_UMIN Differential Revision: https://reviews.llvm.org/D88750
36 lines
1.1 KiB
YAML
36 lines
1.1 KiB
YAML
# RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: aarch64-registered-target
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-unknown"
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define i32 @vector_reductions() {
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ret i32 0
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}
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...
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---
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name: vector_reductions
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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body: |
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bb.0:
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%vec_v2s64:_(<2 x s64>) = IMPLICIT_DEF
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%scalar_s64:_(s64) = IMPLICIT_DEF
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%seq_fadd:_(<2 x s64>) = G_VECREDUCE_SEQ_FADD %scalar_s64, %vec_v2s64
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; CHECK: Bad machine code: Vector reduction requires a scalar destination type
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%dst:_(s64) = G_VECREDUCE_SEQ_FADD %vec_v2s64, %vec_v2s64
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; CHECK: Bad machine code: FADD/FMUL vector reduction requires a scalar 1st operand
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%dst:_(s64) = G_VECREDUCE_SEQ_FADD %scalar_s64, %scalar_s64
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; CHECK: Bad machine code: FADD/FMUL vector reduction must have a vector 2nd operand
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%dst2:_(s64) = G_VECREDUCE_MUL %scalar_s64
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; CHECK: Bad machine code: Vector reduction requires vector source
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...
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