660e34fd38
The PR adds the support optionally enabled/disabled FP-registers to LLDB `RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V builds having no FP-registers, like RV64IMAC or RV64IMACV. To aim this, patch adds `opt_regsets` flags mechanism. It re-works RegisterInfo class to work with flexibly allocated (depending on `opt_regsets` flag) `m_register_sets` and `m_register_infos` vectors instead of statically defined structures. The registration of regsets is being arranged by `m_per_regset_regnum_range` map. The patch flows are spread to `NativeRegisterContextLinux_riscv64` and `RegisterContextCorePOSIX_riscv64` classes, that were tested on: - x86_64 host working with coredumps - RV64GC and RV64IMAC targets working with coredumps and natively in run-time with binaries `EmulateInstructionRISCV` is out of scope of this patch, and its behavior did not change, using maximum set of registers. According testcase built for RV64IMAC (no-FPR) was added to `TestLinuxCore.py`.
95 lines
2.6 KiB
C++
95 lines
2.6 KiB
C++
//===-- NativeRegisterContextLinux_riscv64.h -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#if defined(__riscv) && __riscv_xlen == 64
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#ifndef lldb_NativeRegisterContextLinux_riscv64_h
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#define lldb_NativeRegisterContextLinux_riscv64_h
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#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
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#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
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#include <asm/ptrace.h>
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namespace lldb_private {
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namespace process_linux {
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class NativeProcessLinux;
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class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
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public:
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NativeRegisterContextLinux_riscv64(
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const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
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std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up);
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uint32_t GetRegisterSetCount() const override;
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uint32_t GetUserRegisterCount() const override;
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const RegisterSet *GetRegisterSet(uint32_t set_index) const override;
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Status ReadRegister(const RegisterInfo *reg_info,
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RegisterValue ®_value) override;
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Status WriteRegister(const RegisterInfo *reg_info,
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const RegisterValue ®_value) override;
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Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
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Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
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void InvalidateAllRegisters() override;
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std::vector<uint32_t>
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GetExpeditedRegisters(ExpeditedRegs expType) const override;
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bool RegisterOffsetIsDynamic() const override { return true; }
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protected:
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Status ReadGPR() override;
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Status WriteGPR() override;
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Status ReadFPR() override;
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Status WriteFPR() override;
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void *GetGPRBuffer() override { return &m_gpr; }
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void *GetFPRBuffer() override { return &m_fpr; }
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size_t GetGPRSize() const override { return GetRegisterInfo().GetGPRSize(); }
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size_t GetFPRSize() override { return GetRegisterInfo().GetFPRSize(); }
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private:
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bool m_gpr_is_valid;
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bool m_fpu_is_valid;
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RegisterInfoPOSIX_riscv64::GPR m_gpr;
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RegisterInfoPOSIX_riscv64::FPR m_fpr;
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size_t GetRegContextSize();
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bool IsGPR(unsigned reg) const;
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bool IsFPR(unsigned reg) const;
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uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
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const RegisterInfoPOSIX_riscv64 &GetRegisterInfo() const;
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};
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} // namespace process_linux
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} // namespace lldb_private
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#endif // #ifndef lldb_NativeRegisterContextLinux_riscv64_h
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#endif // defined(__riscv) && __riscv_xlen == 64
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