666ef0db20
At AMD, in an internal audit of our code, we found some corner cases
where we were not quite differentiating targets enough for some old
hardware. This commit is part of fixing that by adding three new
targets:
* The "Oland" and "Hainan" variants of gfx601 are now split out into
gfx602. LLPC (in the GPUOpen driver) and other front-ends could use
that to avoid using the shaderZExport workaround on gfx602.
* One variant of gfx703 is now split out into gfx705. LLPC and other
front-ends could use that to avoid using the
shaderSpiCsRegAllocFragmentation workaround on gfx705.
* The "TongaPro" variant of gfx802 is now split out into gfx805.
TongaPro has a faster 64-bit shift than its former friends in gfx802,
and a subtarget feature could be set up for that to take advantage of
it. This commit does not make that change; it just adds the target.
V2: Add clang changes. Put TargetParser list in order.
V3: AMDGCNGPUs table in TargetParser.cpp needs to be in GPUKind order,
so fix the GPUKind order.
Differential Revision: https://reviews.llvm.org/D88916
Change-Id: Ia901a7157eb2f73ccd9f25dbacec38427312377d
291 lines
11 KiB
C++
291 lines
11 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/TargetParser.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/ARMBuildAttributes.h"
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using namespace llvm;
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using namespace AMDGPU;
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namespace {
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struct GPUInfo {
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StringLiteral Name;
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StringLiteral CanonicalName;
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AMDGPU::GPUKind Kind;
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unsigned Features;
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};
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constexpr GPUInfo R600GPUs[26] = {
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// Name Canonical Kind Features
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// Name
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{{"r600"}, {"r600"}, GK_R600, FEATURE_NONE },
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{{"rv630"}, {"r600"}, GK_R600, FEATURE_NONE },
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{{"rv635"}, {"r600"}, GK_R600, FEATURE_NONE },
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{{"r630"}, {"r630"}, GK_R630, FEATURE_NONE },
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{{"rs780"}, {"rs880"}, GK_RS880, FEATURE_NONE },
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{{"rs880"}, {"rs880"}, GK_RS880, FEATURE_NONE },
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{{"rv610"}, {"rs880"}, GK_RS880, FEATURE_NONE },
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{{"rv620"}, {"rs880"}, GK_RS880, FEATURE_NONE },
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{{"rv670"}, {"rv670"}, GK_RV670, FEATURE_NONE },
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{{"rv710"}, {"rv710"}, GK_RV710, FEATURE_NONE },
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{{"rv730"}, {"rv730"}, GK_RV730, FEATURE_NONE },
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{{"rv740"}, {"rv770"}, GK_RV770, FEATURE_NONE },
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{{"rv770"}, {"rv770"}, GK_RV770, FEATURE_NONE },
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{{"cedar"}, {"cedar"}, GK_CEDAR, FEATURE_NONE },
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{{"palm"}, {"cedar"}, GK_CEDAR, FEATURE_NONE },
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{{"cypress"}, {"cypress"}, GK_CYPRESS, FEATURE_FMA },
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{{"hemlock"}, {"cypress"}, GK_CYPRESS, FEATURE_FMA },
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{{"juniper"}, {"juniper"}, GK_JUNIPER, FEATURE_NONE },
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{{"redwood"}, {"redwood"}, GK_REDWOOD, FEATURE_NONE },
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{{"sumo"}, {"sumo"}, GK_SUMO, FEATURE_NONE },
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{{"sumo2"}, {"sumo"}, GK_SUMO, FEATURE_NONE },
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{{"barts"}, {"barts"}, GK_BARTS, FEATURE_NONE },
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{{"caicos"}, {"caicos"}, GK_CAICOS, FEATURE_NONE },
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{{"aruba"}, {"cayman"}, GK_CAYMAN, FEATURE_FMA },
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{{"cayman"}, {"cayman"}, GK_CAYMAN, FEATURE_FMA },
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{{"turks"}, {"turks"}, GK_TURKS, FEATURE_NONE }
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};
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// This table should be sorted by the value of GPUKind
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// Don't bother listing the implicitly true features
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constexpr GPUInfo AMDGCNGPUs[43] = {
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// Name Canonical Kind Features
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// Name
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{{"gfx600"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32},
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{{"tahiti"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32},
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{{"gfx601"}, {"gfx601"}, GK_GFX601, FEATURE_NONE},
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{{"pitcairn"}, {"gfx601"}, GK_GFX601, FEATURE_NONE},
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{{"verde"}, {"gfx601"}, GK_GFX601, FEATURE_NONE},
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{{"gfx602"}, {"gfx602"}, GK_GFX602, FEATURE_NONE},
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{{"hainan"}, {"gfx602"}, GK_GFX602, FEATURE_NONE},
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{{"oland"}, {"gfx602"}, GK_GFX602, FEATURE_NONE},
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{{"gfx700"}, {"gfx700"}, GK_GFX700, FEATURE_NONE},
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{{"kaveri"}, {"gfx700"}, GK_GFX700, FEATURE_NONE},
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{{"gfx701"}, {"gfx701"}, GK_GFX701, FEATURE_FAST_FMA_F32},
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{{"hawaii"}, {"gfx701"}, GK_GFX701, FEATURE_FAST_FMA_F32},
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{{"gfx702"}, {"gfx702"}, GK_GFX702, FEATURE_FAST_FMA_F32},
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{{"gfx703"}, {"gfx703"}, GK_GFX703, FEATURE_NONE},
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{{"kabini"}, {"gfx703"}, GK_GFX703, FEATURE_NONE},
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{{"mullins"}, {"gfx703"}, GK_GFX703, FEATURE_NONE},
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{{"gfx704"}, {"gfx704"}, GK_GFX704, FEATURE_NONE},
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{{"bonaire"}, {"gfx704"}, GK_GFX704, FEATURE_NONE},
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{{"gfx705"}, {"gfx705"}, GK_GFX705, FEATURE_NONE},
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{{"gfx801"}, {"gfx801"}, GK_GFX801, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"carrizo"}, {"gfx801"}, GK_GFX801, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx802"}, {"gfx802"}, GK_GFX802, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"iceland"}, {"gfx802"}, GK_GFX802, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"tonga"}, {"gfx802"}, GK_GFX802, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx803"}, {"gfx803"}, GK_GFX803, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"fiji"}, {"gfx803"}, GK_GFX803, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"polaris10"}, {"gfx803"}, GK_GFX803, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"polaris11"}, {"gfx803"}, GK_GFX803, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx805"}, {"gfx805"}, GK_GFX805, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"tongapro"}, {"gfx805"}, GK_GFX805, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx810"}, {"gfx810"}, GK_GFX810, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"stoney"}, {"gfx810"}, GK_GFX810, FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx900"}, {"gfx900"}, GK_GFX900, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx902"}, {"gfx902"}, GK_GFX902, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx904"}, {"gfx904"}, GK_GFX904, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx906"}, {"gfx906"}, GK_GFX906, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAM_ECC},
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{{"gfx908"}, {"gfx908"}, GK_GFX908, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_SRAM_ECC},
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{{"gfx909"}, {"gfx909"}, GK_GFX909, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK},
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{{"gfx1010"}, {"gfx1010"}, GK_GFX1010, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK},
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{{"gfx1011"}, {"gfx1011"}, GK_GFX1011, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK},
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{{"gfx1012"}, {"gfx1012"}, GK_GFX1012, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK},
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{{"gfx1030"}, {"gfx1030"}, GK_GFX1030, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32},
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{{"gfx1031"}, {"gfx1031"}, GK_GFX1031, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32},
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};
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const GPUInfo *getArchEntry(AMDGPU::GPUKind AK, ArrayRef<GPUInfo> Table) {
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GPUInfo Search = { {""}, {""}, AK, AMDGPU::FEATURE_NONE };
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auto I = std::lower_bound(Table.begin(), Table.end(), Search,
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[](const GPUInfo &A, const GPUInfo &B) {
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return A.Kind < B.Kind;
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});
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if (I == Table.end())
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return nullptr;
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return I;
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}
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} // namespace
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StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) {
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if (const auto *Entry = getArchEntry(AK, AMDGCNGPUs))
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return Entry->CanonicalName;
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return "";
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}
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StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK) {
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if (const auto *Entry = getArchEntry(AK, R600GPUs))
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return Entry->CanonicalName;
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return "";
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}
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AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU) {
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for (const auto &C : AMDGCNGPUs) {
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if (CPU == C.Name)
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return C.Kind;
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}
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return AMDGPU::GPUKind::GK_NONE;
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}
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AMDGPU::GPUKind llvm::AMDGPU::parseArchR600(StringRef CPU) {
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for (const auto &C : R600GPUs) {
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if (CPU == C.Name)
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return C.Kind;
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}
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return AMDGPU::GPUKind::GK_NONE;
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}
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unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) {
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if (const auto *Entry = getArchEntry(AK, AMDGCNGPUs))
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return Entry->Features;
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return FEATURE_NONE;
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}
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unsigned AMDGPU::getArchAttrR600(GPUKind AK) {
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if (const auto *Entry = getArchEntry(AK, R600GPUs))
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return Entry->Features;
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return FEATURE_NONE;
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}
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void AMDGPU::fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values) {
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// XXX: Should this only report unique canonical names?
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for (const auto &C : AMDGCNGPUs)
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Values.push_back(C.Name);
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}
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void AMDGPU::fillValidArchListR600(SmallVectorImpl<StringRef> &Values) {
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for (const auto &C : R600GPUs)
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Values.push_back(C.Name);
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}
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AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
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AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
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if (AK == AMDGPU::GPUKind::GK_NONE) {
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if (GPU == "generic-hsa")
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return {7, 0, 0};
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if (GPU == "generic")
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return {6, 0, 0};
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return {0, 0, 0};
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}
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switch (AK) {
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case GK_GFX600: return {6, 0, 0};
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case GK_GFX601: return {6, 0, 1};
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case GK_GFX602: return {6, 0, 2};
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case GK_GFX700: return {7, 0, 0};
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case GK_GFX701: return {7, 0, 1};
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case GK_GFX702: return {7, 0, 2};
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case GK_GFX703: return {7, 0, 3};
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case GK_GFX704: return {7, 0, 4};
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case GK_GFX705: return {7, 0, 5};
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case GK_GFX801: return {8, 0, 1};
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case GK_GFX802: return {8, 0, 2};
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case GK_GFX803: return {8, 0, 3};
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case GK_GFX805: return {8, 0, 5};
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case GK_GFX810: return {8, 1, 0};
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case GK_GFX900: return {9, 0, 0};
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case GK_GFX902: return {9, 0, 2};
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case GK_GFX904: return {9, 0, 4};
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case GK_GFX906: return {9, 0, 6};
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case GK_GFX908: return {9, 0, 8};
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case GK_GFX909: return {9, 0, 9};
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case GK_GFX1010: return {10, 1, 0};
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case GK_GFX1011: return {10, 1, 1};
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case GK_GFX1012: return {10, 1, 2};
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case GK_GFX1030: return {10, 3, 0};
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case GK_GFX1031: return {10, 3, 1};
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default: return {0, 0, 0};
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}
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}
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StringRef AMDGPU::getCanonicalArchName(const Triple &T, StringRef Arch) {
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assert(T.isAMDGPU());
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auto ProcKind = T.isAMDGCN() ? parseArchAMDGCN(Arch) : parseArchR600(Arch);
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if (ProcKind == GK_NONE)
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return StringRef();
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return T.isAMDGCN() ? getArchNameAMDGCN(ProcKind) : getArchNameR600(ProcKind);
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}
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namespace llvm {
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namespace RISCV {
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struct CPUInfo {
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StringLiteral Name;
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CPUKind Kind;
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unsigned Features;
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StringLiteral DefaultMarch;
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bool is64Bit() const { return (Features & FK_64BIT); }
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};
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constexpr CPUInfo RISCVCPUInfo[] = {
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) \
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{NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
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#include "llvm/Support/RISCVTargetParser.def"
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};
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bool checkCPUKind(CPUKind Kind, bool IsRV64) {
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if (Kind == CK_INVALID)
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return false;
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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CPUKind parseCPUKind(StringRef CPU) {
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return llvm::StringSwitch<CPUKind>(CPU)
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#include "llvm/Support/RISCVTargetParser.def"
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.Default(CK_INVALID);
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}
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StringRef getMArchFromMcpu(StringRef CPU) {
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CPUKind Kind = parseCPUKind(CPU);
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
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}
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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}
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// Get all features except standard extension feature
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bool getCPUFeaturesExceptStdExt(CPUKind Kind,
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std::vector<StringRef> &Features) {
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unsigned CPUFeatures = RISCVCPUInfo[static_cast<unsigned>(Kind)].Features;
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if (CPUFeatures == FK_INVALID)
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return false;
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if (CPUFeatures & FK_64BIT)
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Features.push_back("+64bit");
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else
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Features.push_back("-64bit");
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return true;
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}
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} // namespace RISCV
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} // namespace llvm
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