Simon Pilgrim 00e5676cf6 [LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

2020-09-14 11:09:43 +01:00

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CMakeLists.txt

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DAGCombiner.cpp

[SelectionDAG] Move ISD:PARITY formation from DAGCombine to SimplifyDemandedBits.

2020-09-13 21:04:13 -07:00

FastISel.cpp

[FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel

2020-08-04 14:42:53 -05:00

FunctionLoweringInfo.cpp

[Statepoint] Consolidate relocation type tracking [NFC]

2020-07-29 11:45:31 -07:00

InstrEmitter.cpp

[Statepoints] Properly handle const base pointer.

2020-09-09 14:07:00 +07:00

InstrEmitter.h

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LegalizeDAG.cpp

[LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

2020-09-14 11:09:43 +01:00

LegalizeFloatTypes.cpp

[SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.:

2020-09-08 15:27:21 -07:00

LegalizeIntegerTypes.cpp

[SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.

2020-09-12 11:42:18 -07:00

LegalizeTypes.cpp

[CodeGen] Replace calls to getVectorNumElements() in DAGTypeLegalizer::SetSplitVector

2020-07-10 08:29:17 +01:00

LegalizeTypes.h

[SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.

2020-09-12 11:42:18 -07:00

LegalizeTypesGeneric.cpp

[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize

2020-08-11 12:17:10 +01:00

LegalizeVectorOps.cpp

[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.

2020-08-07 15:09:24 +02:00

LegalizeVectorTypes.cpp

[CodeGen] Fix bug in IncrementPointer

2020-09-14 08:03:55 +01:00

LLVMBuild.txt

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ResourcePriorityQueue.cpp

ResourcePriorityQueue.h - reduce unnecessary includes to forward declarations. NFC.

2020-05-26 19:22:14 +01:00

ScheduleDAGFast.cpp

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ScheduleDAGRRList.cpp

[ScheduleDAGRRList] Pacify overload mismatch in std::min.

2020-07-23 11:56:50 +01:00

ScheduleDAGSDNodes.cpp

[Statepoints] Support lowering gc relocations to virtual registers

2020-07-25 14:26:05 -07:00

ScheduleDAGSDNodes.h

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ScheduleDAGVLIW.cpp

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SDNodeDbgValue.h

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SelectionDAG.cpp

[SelectionDAG] Move ISD:PARITY formation from DAGCombine to SimplifyDemandedBits.

2020-09-13 21:04:13 -07:00

SelectionDAGAddressAnalysis.cpp

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SelectionDAGBuilder.cpp

[SelectionDAGBuilder] Remove Unnecessary FastMathFlags temporary. Use SDNodeFlags instead. NFCI

2020-09-08 15:50:12 -07:00

SelectionDAGBuilder.h

[SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.:

2020-09-08 15:27:21 -07:00

SelectionDAGDumper.cpp

[SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.

2020-09-12 11:42:18 -07:00

SelectionDAGISel.cpp

[AArch64][SVE] Preserve full vector regs over EH edge.

2020-09-02 10:54:18 +01:00

SelectionDAGPrinter.cpp

Utility to dump .dot representation of SelectionDAG without firing viewer

2020-06-04 11:51:48 +05:30

SelectionDAGTargetInfo.cpp

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StatepointLowering.cpp

[Statepoints] Update DAG root after emitting statepoint.

2020-09-09 20:22:10 +07:00

StatepointLowering.h

[Statepoint] Consolidate relocation type tracking [NFC]

2020-07-29 11:45:31 -07:00

TargetLowering.cpp

[SelectionDAG] Move ISD:PARITY formation from DAGCombine to SimplifyDemandedBits.

2020-09-13 21:04:13 -07:00