93ef145862
As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
49 lines
908 B
YAML
49 lines
908 B
YAML
# RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: INTERVALS
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# CHECK: %0
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# CHECK-LABEL: Machine code for function test0:
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# CHECK: INTERVALS
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# CHECK: %0
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# CHECK-LABEL: Machine code for function test1:
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--- |
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define amdgpu_kernel void @test0() { ret void }
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define amdgpu_kernel void @test1() { ret void }
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...
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---
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name: test0
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit %0
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S_NOP 0, implicit-def undef %0.sub0
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S_NOP 0, implicit %0
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...
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---
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name: test1
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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S_NOP 0, implicit-def undef %0.sub0
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S_BRANCH %bb.3
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bb.2:
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S_NOP 0, implicit-def %0
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S_BRANCH %bb.3
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bb.3:
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S_NOP 0
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S_NOP 0, implicit %0
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...
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