Florian Hahn 6108d50aed [VPlan] Add ReductionStartVector VPInstruction. (#142290) ...

Add a new VPInstruction::ReductionStartVector opcode to create the start
values for wide reductions. This more accurately models the start value
creation in VPlan and simplifies VPReductionPHIRecipe::execute. Down the
line it also allows removing VPReductionPHIRecipe::RdxDesc.

PR: https://github.com/llvm/llvm-project/pull/142290

2025-06-09 20:59:12 +01:00

..

bf16.ll

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blend-any-of-reduction-cost.ll

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blocks-with-dead-instructions.ll

[VPlan] Introduce constant folder in simplifyRecipe (#125365)

2025-05-20 14:16:01 +01:00

dead-ops-cost.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

defaults.ll

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divrem.ll

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evl-compatible-loops.ll

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evl-iv-simplify.ll

[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)

2025-05-14 13:49:50 -07:00

f16.ll

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first-order-recurrence-scalable-vf1.ll

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fminimumnum.ll

[RISCV] Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (#135727)

2025-04-27 19:10:02 +08:00

force-vect-msg.ll

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illegal-type.ll

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induction-costs.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

inloop-reduction.ll

[LoopVectorizer] Prune VFs based on plan register pressure (#132190)

2025-05-19 13:27:17 +01:00

interleaved-accesses-zve32x.ll

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interleaved-accesses.ll

[LV] Regenerate UTC variable names in RISCV/interleaved-accesses.ll. NFC

2025-06-04 01:07:32 +01:00

interleaved-cost.ll

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interleaved-masked-access.ll

[RISCV][LV] Add tests for masked interleaved access

2025-06-09 09:32:39 -07:00

lit.local.cfg

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lmul.ll

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low-trip-count.ll

[VPlan] Use InstSimplifyFolder instead of TargetFolder (#141222)

2025-05-28 11:00:14 +02:00

mask-index-type.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

masked_gather_scatter.ll

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only-compute-cost-for-vplan-vfs.ll

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ordered-reduction.ll

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partial-reduce-dot-product.ll

[RISCV][TTI] Adjust costing in getPartialReductionCost for zvqdotq (#141430)

2025-05-26 08:23:56 -07:00

pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[VPlan] Use VPlan operand order for VPBlendRecipes. (#139475)

2025-05-14 14:56:35 +01:00

pr88802.ll

[VPlan] Use VPlan operand order for VPBlendRecipes. (#139475)

2025-05-14 14:56:35 +01:00

preserve-dbg-loc.ll

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reg-usage-bf16.ll

[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). (#135673)

2025-06-02 17:40:50 +01:00

reg-usage-f16.ll

[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). (#135673)

2025-06-02 17:40:50 +01:00

reg-usage.ll

[LV] Move VPlan-based calculateRegisterUsage to VPlanAnalysis (NFC). (#135673)

2025-06-02 17:40:50 +01:00

remark-reductions.ll

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riscv-interleaved.ll

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riscv-unroll.ll

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riscv-vector-reverse-output.ll

[LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)

2025-04-14 14:17:39 +08:00

riscv-vector-reverse.ll

[VPlan] Use regular phi printing for resume phis.

2025-06-07 21:49:54 +01:00

safe-dep-distance.ll

[LAA] Make sure MaxVF for Store-Load forward safe dep distances is pow2.

2025-04-12 20:05:37 +01:00

scalable-basics.ll

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scalable-reductions.ll

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scalable-tailfold.ll

[VPlan] Add initial CFG simplification, removing BranchOnCond true. (#106748)

2025-04-04 15:44:26 +01:00

scalable-vf-hint.ll

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select-cmp-reduction.ll

Reapply "[VPlan] Fold NOT into predicate of wide compares." (#130347)

2025-04-28 20:01:37 +01:00

select-invariant-cond-cost.ll

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short-trip-count.ll

[VPlan] Use InstSimplifyFolder instead of TargetFolder (#141222)

2025-05-28 11:00:14 +02:00

strided-accesses.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

tail-folding-cost.ll

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truncate-to-minimal-bitwidth-cost.ll

[VPlan] Introduce constant folder in simplifyRecipe (#125365)

2025-05-20 14:16:01 +01:00

truncate-to-minimal-bitwidth-evl-crash.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

type-info-cache-evl-crash.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

uniform-load-store.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

unroll-in-loop-vectorizer.ll

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veclib-function-calls.ll

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vectorize-force-tail-with-evl-bin-unary-ops-args.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-call-intrinsics.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-cast-intrinsics.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-cond-reduction.ll

[VPlan] Add ReductionStartVector VPInstruction. (#142290)

2025-06-09 20:59:12 +01:00

vectorize-force-tail-with-evl-div.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-fixed-order-recurrence.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-gather-scatter.ll

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vectorize-force-tail-with-evl-inloop-reduction.ll

[NFC][LLVM][Instrumentation][LoopVectorize] Regenerate test checks.

2025-06-05 11:38:30 +00:00

vectorize-force-tail-with-evl-interleave.ll

[VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (#129508)

2025-05-08 18:47:44 +08:00

vectorize-force-tail-with-evl-intermediate-store.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-iv32.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-known-no-overflow.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-masked-loadstore.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-no-masking.ll

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vectorize-force-tail-with-evl-ordered-reduction.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-force-tail-with-evl-reduction-cost.ll

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vectorize-force-tail-with-evl-reduction.ll

[VPlan] Add ReductionStartVector VPInstruction. (#142290)

2025-06-09 20:59:12 +01:00

vectorize-force-tail-with-evl-reverse-load-store.ll

[NFC][LLVM][Instrumentation][LoopVectorize] Regenerate test checks.

2025-06-05 11:38:30 +00:00

vectorize-force-tail-with-evl-safe-dep-distance.ll

[NFC][LLVM][Instrumentation][LoopVectorize] Regenerate test checks.

2025-06-05 11:38:30 +00:00

vectorize-force-tail-with-evl-uniform-store.ll

[LV][EVL] Attach a new metadata on EVL vectorized loops (#131000)

2025-05-06 10:06:37 -07:00

vectorize-vp-intrinsics.ll

[NFC][LLVM][Instrumentation][LoopVectorize] Regenerate test checks.

2025-06-05 11:38:30 +00:00

vf-will-not-generate-any-vector-insts.ll

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vplan-vp-call-intrinsics.ll

[VPlan] Introduce VPInstructionWithType, use instead of VPScalarCast(NFC) (#129706)

2025-04-10 22:30:40 +01:00

vplan-vp-cast-intrinsics.ll

[VPlan] Introduce VPInstructionWithType, use instead of VPScalarCast(NFC) (#129706)

2025-04-10 22:30:40 +01:00

vplan-vp-intrinsics-fixed-order-recurrence.ll

[VPlan] Use EMIT-SCALAR for single-scalar VPPhis (NFC).

2025-05-29 11:20:07 +01:00

vplan-vp-intrinsics-reduction.ll

[VPlan] Add ReductionStartVector VPInstruction. (#142290)

2025-06-09 20:59:12 +01:00

vplan-vp-intrinsics.ll

[VPlan] Introduce VPInstructionWithType, use instead of VPScalarCast(NFC) (#129706)

2025-04-10 22:30:40 +01:00

vplan-vp-select-intrinsics.ll

[VPlan] Use EMIT-SCALAR for single-scalar VPPhis (NFC).

2025-05-29 11:20:07 +01:00

zvl32b.ll

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