82aac878be
Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
281 lines
11 KiB
C++
281 lines
11 KiB
C++
//===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the VE Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/VEMCTargetDesc.h"
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#include "TargetInfo/VETargetInfo.h"
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#include "VE.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "ve-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// A disassembler class for VE.
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class VEDisassembler : public MCDisassembler {
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public:
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VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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virtual ~VEDisassembler() {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // namespace
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static MCDisassembler *createVEDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new VEDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeVEDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheVETarget(),
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createVEDisassembler);
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}
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static const unsigned I32RegDecoderTable[] = {
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VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
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VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
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VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
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VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
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VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
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VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
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VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
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VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
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VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
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VE::SW63};
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static const unsigned I64RegDecoderTable[] = {
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VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
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VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13,
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VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,
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VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,
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VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,
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VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,
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VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,
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VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,
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VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,
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VE::SX63};
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static const unsigned F32RegDecoderTable[] = {
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VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
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VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
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VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
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VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
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VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
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VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
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VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
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VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
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VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
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VE::SF63};
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static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 63)
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return MCDisassembler::Fail;
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unsigned Reg = I32RegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 63)
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return MCDisassembler::Fail;
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unsigned Reg = I64RegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 63)
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return MCDisassembler::Fail;
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unsigned Reg = F32RegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder);
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#include "VEGenDisassemblerTables.inc"
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/// Read four bytes from the ArrayRef and return 32 bit word.
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static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint64_t &Insn,
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bool IsLittleEndian) {
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// We want to read exactly 8 Bytes of data.
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if (Bytes.size() < 8) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = IsLittleEndian
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? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
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((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) |
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((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) |
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((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56)
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: ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) |
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((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) |
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((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) |
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((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56);
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return MCDisassembler::Success;
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}
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DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CStream) const {
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uint64_t Insn;
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bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
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DecodeStatus Result =
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readInstruction64(Bytes, Address, Size, Insn, isLittleEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 8;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
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const void *Decoder) {
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unsigned sy = fieldFromInstruction(insn, 40, 7);
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bool cy = fieldFromInstruction(insn, 47, 1);
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unsigned sz = fieldFromInstruction(insn, 32, 7);
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bool cz = fieldFromInstruction(insn, 39, 1);
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uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
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DecodeStatus status;
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// Decode sz.
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if (cz) {
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status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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} else {
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MI.addOperand(MCOperand::createImm(0));
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}
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// Decode sy.
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if (cy) {
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status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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} else {
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MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
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}
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// Decode simm32.
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MI.addOperand(MCOperand::createImm(simm32));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
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const void *Decoder, bool isLoad,
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DecodeFunc DecodeSX) {
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unsigned sx = fieldFromInstruction(insn, 48, 7);
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DecodeStatus status;
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if (isLoad) {
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status = DecodeSX(MI, sx, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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status = DecodeASX(MI, insn, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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if (!isLoad) {
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status = DecodeSX(MI, sx, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
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}
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static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
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}
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static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
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}
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static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);
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}
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static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
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}
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static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
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}
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static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
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const void *Decoder) {
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uint64_t tgt = SignExtend64<7>(insn);
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MI.addOperand(MCOperand::createImm(tgt));
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return MCDisassembler::Success;
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}
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