Files
clang-p2996/llvm/test/CodeGen/AArch64
Cullen Rhodes 672b62ea21 [AArch64][SVE] Custom lowering of floating-point reductions
Summary:
This patch implements custom floating-point reduction ISD nodes that
have vector results, which are used to lower the following intrinsics:

    * llvm.aarch64.sve.fadda
    * llvm.aarch64.sve.faddv
    * llvm.aarch64.sve.fmaxv
    * llvm.aarch64.sve.fmaxnmv
    * llvm.aarch64.sve.fminv
    * llvm.aarch64.sve.fminnmv

SVE reduction instructions keep their result within a vector register,
with all other bits set to zero.

Changes in this patch were implemented by Paul Walker and Sander de
Smalen.

Reviewers: sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D78723
2020-04-30 10:18:40 +00:00
..
2019-10-08 13:23:57 +00:00
2020-02-03 11:01:05 +01:00
2019-12-05 18:10:06 +00:00
2020-02-23 19:13:13 +00:00