0d23ebe888
Summary: GCNSchedStrategy re-uses most of GenericScheduler, it's just uses a different method to compute the excess and critical register pressure limits. It's not enabled by default, to enable it you need to pass -misched=gcn to llc. Shader DB stats: 32464 shaders in 17874 tests Totals: SGPRS: 1542846 -> 1643125 (6.50 %) VGPRS: 1005595 -> 904653 (-10.04 %) Spilled SGPRs: 29929 -> 27745 (-7.30 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 36688188 -> 37034900 (0.95 %) bytes LDS: 1913 -> 1913 (0.00 %) blocks Max Waves: 254101 -> 265125 (4.34 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 1338220 -> 1438499 (7.49 %) VGPRS: 886221 -> 785279 (-11.39 %) Spilled SGPRs: 29869 -> 27685 (-7.31 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 34315716 -> 34662428 (1.01 %) bytes LDS: 1551 -> 1551 (0.00 %) blocks Max Waves: 188127 -> 199151 (5.86 %) Wait states: 0 -> 0 (0.00 %) Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23688 llvm-svn: 279995
107 lines
3.6 KiB
LLVM
107 lines
3.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
|
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
|
|
|
|
declare double @llvm.ceil.f64(double) nounwind readnone
|
|
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
|
|
declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
|
|
declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
|
|
declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
|
|
declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
|
|
|
|
; FUNC-LABEL: {{^}}fceil_f64:
|
|
; CI: v_ceil_f64_e32
|
|
; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
|
|
; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
|
|
; FIXME: We should be using s_addk_i32 here, but the reg allocation hints
|
|
; are not always followed.
|
|
; SI-DAG: s_add_i32 [[SEXP0:s[0-9]+]], [[SEXP]], 0xfffffc01
|
|
; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP0]]
|
|
; SI-DAG: s_not_b64
|
|
; SI-DAG: s_and_b64
|
|
; SI-DAG: cmp_gt_i32
|
|
; SI-DAG: cndmask_b32
|
|
; SI-DAG: cndmask_b32
|
|
; SI-DAG: cmp_lt_i32
|
|
; SI-DAG: cndmask_b32
|
|
; SI-DAG: cndmask_b32
|
|
; SI-DAG: v_cmp_lt_f64
|
|
; SI-DAG: v_cmp_lg_f64
|
|
; SI-DAG: v_cndmask_b32
|
|
; SI: v_cndmask_b32
|
|
; SI: v_add_f64
|
|
; SI: s_endpgm
|
|
define void @fceil_f64(double addrspace(1)* %out, double %x) {
|
|
%y = call double @llvm.ceil.f64(double %x) nounwind readnone
|
|
store double %y, double addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fceil_v2f64:
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
|
|
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
|
|
store <2 x double> %y, <2 x double> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME-FUNC-LABEL: {{^}}fceil_v3f64:
|
|
; FIXME-CI: v_ceil_f64_e32
|
|
; FIXME-CI: v_ceil_f64_e32
|
|
; FIXME-CI: v_ceil_f64_e32
|
|
; define void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
|
|
; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
|
|
; store <3 x double> %y, <3 x double> addrspace(1)* %out
|
|
; ret void
|
|
; }
|
|
|
|
; FUNC-LABEL: {{^}}fceil_v4f64:
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
|
|
%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
|
|
store <4 x double> %y, <4 x double> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fceil_v8f64:
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
|
|
%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
|
|
store <8 x double> %y, <8 x double> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fceil_v16f64:
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
; CI: v_ceil_f64_e32
|
|
define void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
|
|
%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
|
|
store <16 x double> %y, <16 x double> addrspace(1)* %out
|
|
ret void
|
|
}
|