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clang-p2996/llvm/test/CodeGen/NVPTX
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Justin Lebar d13880a750 [NVPTX] Switch nvptx-use-infer-addrspace to true. 
Summary:
This switches us to use a different, more powerful algorithm for address
space inference.  I've tested this locally and it seems to work great.
Once we're more confident in it, we can remove the old pass altogether.

Reviewers: jingyue

Subscribers: llvm-commits, tra, jholewinski

Differential Revision: https://reviews.llvm.org/D23694

llvm-svn: 279317
2016-08-19 20:46:45 +00:00
..
access-non-generic.ll
[NVPTX] Switch nvptx-use-infer-addrspace to true.
2016-08-19 20:46:45 +00:00
add-128bit.ll
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addrspacecast-gvar.ll
[NVPTX] Handle addrspacecast constant expressions in aggregate initializers
2015-04-28 17:18:30 +00:00
addrspacecast.ll
[NVPTX] Switch nvptx-use-infer-addrspace to true.
2016-08-19 20:46:45 +00:00
aggr-param.ll
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aggregate-return.ll
[NVPTX] deal with all aggregate return types.
2016-07-20 18:39:52 +00:00
alias.ll
[CUDA] Die gracefully when trying to output an LLVM alias.
2016-01-23 21:12:20 +00:00
annotations.ll
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arg-lowering.ll
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arithmetic-fp-sm20.ll
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arithmetic-int.ll
[NVPTX] expand mul_lohi to mul_lo and mul_hi
2016-01-22 19:47:26 +00:00
atomics.ll
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bfe.ll
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branch-fold.ll
Roll forward r242871
2015-07-29 18:59:09 +00:00
bug17709.ll
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bug21465.ll
[NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.
2016-07-20 21:44:07 +00:00
bug22246.ll
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bug22322.ll
NVPTX: Remove the legacy ptx intrinsics
2016-07-07 16:40:17 +00:00
bug26185-2.ll
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
2016-05-02 18:12:02 +00:00
bug26185.ll
[NVPTX] Handle ldg created from sign-/zero-extended load
2016-04-05 12:38:01 +00:00
bypass-div.ll
Use 32-bit divides instead of 64-bit divides where possible.
2015-08-11 22:16:34 +00:00
call-with-alloca-buffer.ll
Fix NVPTX/call-with-alloca-buffer.ll after r276777.
2016-07-26 18:28:33 +00:00
callchain.ll
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calling-conv.ll
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combine-min-max.ll
[NVPTX] Let NVPTX backend detect integer min and max patterns.
2015-08-26 23:22:02 +00:00
compare-int.ll
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constant-vectors.ll
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convergent-mir-call.ll
[NVPTX] Use different, convergent MIs for convergent calls.
2016-03-01 19:24:03 +00:00
convert-fp.ll
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convert-int-sm20.ll
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ctlz.ll
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ctpop.ll
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cttz.ll
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debug-file-loc.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
disable-opt.ll
[NVPTX] Disable performance optimizations when OptLevel==None
2016-02-04 04:15:36 +00:00
div-ri.ll
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envreg.ll
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extloadv.ll
[NVPTX] expand extload/truncstore for vectors of floats
2015-07-01 21:32:42 +00:00
fast-math.ll
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fma-assoc.ll
SelectionDAG: Prefer to combine multiplication with less uses for fma
2015-08-11 19:21:46 +00:00
fma-disable.ll
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fma.ll
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fp16.ll
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fp-contract.ll
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fp-literals.ll
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function-align.ll
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generic-to-nvvm-ir.ll
[NVPTX] remove unnecessary named metadata update that happens to break debug info.
2016-08-02 20:58:24 +00:00
generic-to-nvvm.ll
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global-addrspace.ll
[NVPTX] Allow undef value as global initializer
2015-08-22 05:40:26 +00:00
global-ctor-empty.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ctor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-dtor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ordering.ll
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global-visibility.ll
[NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
2016-01-15 23:57:53 +00:00
globals_init.ll
The constant initialization for globals in NVPTX is generated as an
2015-06-09 16:29:34 +00:00
globals_lowering.ll
Force relocation mode to be default, regardless of what is passed to the backend.
2015-06-30 17:18:00 +00:00
gvar-init.ll
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half.ll
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i1-global.ll
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i1-int-to-fp.ll
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i1-param.ll
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i8-param.ll
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imad.ll
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implicit-def.ll
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inline-asm.ll
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intrin-nocapture.ll
Reapply 239795 - [InstCombine] Propagate non-null facts to call parameters
2015-06-16 20:24:25 +00:00
intrinsic-old.ll
NVPTX: Remove the legacy ptx intrinsics
2016-07-07 16:40:17 +00:00
intrinsics.ll
[NVPTX] Added missing test case for llvm.nvvm.sqrt.f NVPTX intrinsic
2015-06-23 18:22:17 +00:00
isspacep.ll
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ld-addrspace.ll
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ld-generic.ll
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ldparam-v4.ll
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ldu-i8.ll
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ldu-ldg.ll
…
ldu-reg-plus-offset.ll
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lit.local.cfg
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load-sext-i1.ll
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load-with-non-coherent-cache.ll
[NVPTX] Use LDG for pointer induction variables.
2015-08-05 23:11:57 +00:00
LoadStoreVectorizer.ll
[NVPTX] Enable the load-store vectorizer on nvptx.
2016-07-20 22:11:36 +00:00
local-stack-frame.ll
[NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
2015-07-01 20:08:06 +00:00
loop-vectorize.ll
[NVPTX] declare no vector registers
2015-07-10 04:31:56 +00:00
lower-aggr-copies.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
lower-alloca.ll
Add NVPTXLowerAlloca pass to convert alloca'ed memory to local address
2015-06-17 22:31:02 +00:00
lower-kernel-ptr-arg.ll
[NVPTX] Improve lowering of byval args of device functions.
2016-07-20 18:39:47 +00:00
machine-sink.ll
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MachineSink-call.ll
[NVPTX] Annotate call machine instructions as calls.
2016-02-17 17:46:50 +00:00
MachineSink-convergent.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
managed.ll
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misaligned-vector-ldst.ll
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module-inline-asm.ll
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mulwide.ll
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noduplicate-syncthreads.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
nounroll.ll
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nvcl-param-align.ll
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nvvm-reflect-module-flag.ll
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
2016-04-01 01:09:07 +00:00
nvvm-reflect.ll
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param-align.ll
[NVPTX] Make sure we adjust alignment at all call sites
2016-07-18 21:58:48 +00:00
pr13291-i1-store.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
pr16278.ll
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pr17529.ll
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refl1.ll
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reg-copy.ll
[NVPTX] allow register copy between float and int
2015-08-01 18:02:12 +00:00
reg-types.ll
[NVPTX] Use untyped (.b) integer registers in PTX.
2016-08-12 22:02:19 +00:00
rotate.ll
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rsqrt.ll
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sched1.ll
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sched2.ll
…
sext-in-reg.ll
…
sext-params.ll
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shfl.ll
[NVPTX] Add intrinsics for shfl instructions.
2016-06-09 20:04:08 +00:00
shift-parts.ll
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simple-call.ll
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sm-version-20.ll
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sm-version-21.ll
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sm-version-30.ll
…
sm-version-32.ll
…
sm-version-35.ll
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sm-version-37.ll
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sm-version-50.ll
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sm-version-52.ll
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sm-version-53.ll
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sm-version-60.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
sm-version-61.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
sm-version-62.ll
[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
2016-07-06 21:06:10 +00:00
speculative-execution-divergent-target.ll
Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
2016-04-15 01:20:52 +00:00
st-addrspace.ll
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st-generic.ll
…
surf-read-cuda.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
surf-read.ll
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surf-write-cuda.ll
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surf-write.ll
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symbol-naming.ll
Have a single way for creating unique value names.
2015-11-22 00:16:24 +00:00
TailDuplication-convergent.ll
NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
2016-07-06 20:02:45 +00:00
tex-read-cuda.ll
[NVPTX] roll forward r239082
2015-06-04 21:28:26 +00:00
tex-read.ll
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texsurf-queries.ll
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tuple-literal.ll
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vec8.ll
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vec-param-load.ll
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vector-args.ll
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vector-call.ll
Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI
2015-08-10 19:01:27 +00:00
vector-compare.ll
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vector-global.ll
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vector-loads.ll
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vector-select.ll
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vector-stores.ll
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weak-global.ll
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weak-linkage.ll
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zeroext-32bit.ll
Only emit extension for zeroext/signext arguments if type is < 32 bits
2016-06-27 20:22:22 +00:00