61510b51c3
This reverts commit 9c319d5bb4.
Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.
279 lines
7.8 KiB
LLVM
279 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; ====== Scalar Tests =====
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; ====== Scalar bswap.i16 Tests =====
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define i16 @bswap_i16_to_i16_anyext(i16 %a){
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; CHECK-SD-LABEL: bswap_i16_to_i16_anyext:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: rev16 w0, w0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bswap_i16_to_i16_anyext:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: rev w8, w0
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; CHECK-GI-NEXT: lsr w0, w8, #16
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; CHECK-GI-NEXT: ret
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%3 = call i16 @llvm.bswap.i16(i16 %a)
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ret i16 %3
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}
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declare i16 @llvm.bswap.i16(i16)
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; The zext here is optimised to an any_extend during isel.
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define i64 @bswap_i16_to_i64_anyext(i16 %a) {
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; CHECK-SD-LABEL: bswap_i16_to_i64_anyext:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-SD-NEXT: rev16 x8, x0
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; CHECK-SD-NEXT: lsl x0, x8, #48
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bswap_i16_to_i64_anyext:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: rev w8, w0
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; CHECK-GI-NEXT: lsr w8, w8, #16
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; CHECK-GI-NEXT: and x8, x8, #0xffff
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; CHECK-GI-NEXT: lsl x0, x8, #48
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; CHECK-GI-NEXT: ret
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%3 = call i16 @llvm.bswap.i16(i16 %a)
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%4 = zext i16 %3 to i64
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%5 = shl i64 %4, 48
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ret i64 %5
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}
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; The zext here is optimised to an any_extend during isel..
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define i128 @bswap_i16_to_i128_anyext(i16 %a) {
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; CHECK-SD-LABEL: bswap_i16_to_i128_anyext:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, w0
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; CHECK-SD-NEXT: mov x0, xzr
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; CHECK-SD-NEXT: rev w8, w8
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; CHECK-SD-NEXT: lsr w8, w8, #16
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; CHECK-SD-NEXT: lsl x1, x8, #48
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bswap_i16_to_i128_anyext:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, w0
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; CHECK-GI-NEXT: mov x0, xzr
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; CHECK-GI-NEXT: rev w8, w8
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; CHECK-GI-NEXT: lsr w8, w8, #16
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; CHECK-GI-NEXT: and x8, x8, #0xffff
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; CHECK-GI-NEXT: lsl x1, x8, #48
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; CHECK-GI-NEXT: ret
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%3 = call i16 @llvm.bswap.i16(i16 %a)
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%4 = zext i16 %3 to i128
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%5 = shl i128 %4, 112
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ret i128 %5
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}
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define i32 @bswap_i16_to_i32_zext(i16 %a){
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; CHECK-LABEL: bswap_i16_to_i32_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev w8, w0
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%3 = call i16 @llvm.bswap.i16(i16 %a)
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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; ====== Other scalar bswap tests =====
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define i32 @bswap_i32(i32 %a){
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; CHECK-LABEL: bswap_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev w0, w0
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; CHECK-NEXT: ret
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%3 = call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %3
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}
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declare i32 @llvm.bswap.i32(i32)
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define i64 @bswap_i64(i64 %a){
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; CHECK-LABEL: bswap_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev x0, x0
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; CHECK-NEXT: ret
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%3 = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %3
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}
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declare i64 @llvm.bswap.i64(i64)
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define i128 @bswap_i128(i128 %a){
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; CHECK-LABEL: bswap_i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev x8, x1
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; CHECK-NEXT: rev x1, x0
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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%3 = call i128 @llvm.bswap.i128(i128 %a)
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ret i128 %3
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}
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declare i128 @llvm.bswap.i128(i128)
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; ===== Legal Vector Type Tests =====
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define <4 x i16> @bswap_v4i16(<4 x i16> %a){
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; CHECK-LABEL: bswap_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev16 v0.8b, v0.8b
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; CHECK-NEXT: ret
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%3 = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %a)
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ret <4 x i16> %3
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}
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declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
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define <8 x i16> @bswap_v8i16(<8 x i16> %a){
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; CHECK-LABEL: bswap_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev16 v0.16b, v0.16b
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; CHECK-NEXT: ret
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%3 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a)
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ret <8 x i16> %3
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}
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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define <2 x i32> @bswap_v2i32(<2 x i32> %a){
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; CHECK-LABEL: bswap_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.8b, v0.8b
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; CHECK-NEXT: ret
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%3 = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
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ret <2 x i32> %3
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}
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declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)
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define <4 x i32> @bswap_v4i32(<4 x i32> %a){
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; CHECK-LABEL: bswap_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.16b, v0.16b
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; CHECK-NEXT: ret
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%3 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)
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ret <4 x i32> %3
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}
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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define <2 x i64> @bswap_v2i64(<2 x i64> %a){
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; CHECK-LABEL: bswap_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev64 v0.16b, v0.16b
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; CHECK-NEXT: ret
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%3 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
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ret <2 x i64> %3
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}
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
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; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====
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define <2 x i16> @bswap_v2i16(<2 x i16> %a){
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; CHECK-SD-LABEL: bswap_v2i16:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: rev32 v0.8b, v0.8b
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; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bswap_v2i16:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
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; CHECK-GI-NEXT: rev16 v0.8b, v0.8b
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; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-GI-NEXT: ret
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entry:
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%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
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ret <2 x i16> %res
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}
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declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>)
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define <16 x i16> @bswap_v16i16(<16 x i16> %a){
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; CHECK-LABEL: bswap_v16i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev16 v0.16b, v0.16b
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; CHECK-NEXT: rev16 v1.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
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ret <16 x i16> %res
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}
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declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
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define <1 x i32> @bswap_v1i32(<1 x i32> %a){
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; CHECK-SD-LABEL: bswap_v1i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: rev32 v0.8b, v0.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bswap_v1i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fmov w8, s0
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; CHECK-GI-NEXT: rev w8, w8
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; CHECK-GI-NEXT: mov v0.s[0], w8
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-GI-NEXT: ret
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entry:
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%res = call <1 x i32> @llvm.bswap.v1i32(<1 x i32> %a)
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ret <1 x i32> %res
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}
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declare <1 x i32> @llvm.bswap.v1i32(<1 x i32>)
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define <8 x i32> @bswap_v8i32(<8 x i32> %a){
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; CHECK-LABEL: bswap_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev32 v0.16b, v0.16b
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; CHECK-NEXT: rev32 v1.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
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define <4 x i64> @bswap_v4i64(<4 x i64> %a){
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; CHECK-LABEL: bswap_v4i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev64 v0.16b, v0.16b
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; CHECK-NEXT: rev64 v1.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
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; ===== Vectors with Non-Pow 2 Widths =====
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define <3 x i16> @bswap_v3i16(<3 x i16> %a){
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; CHECK-LABEL: bswap_v3i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev16 v0.8b, v0.8b
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; CHECK-NEXT: ret
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entry:
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%res = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %a)
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ret <3 x i16> %res
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}
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declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>)
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define <7 x i16> @bswap_v7i16(<7 x i16> %a){
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; CHECK-LABEL: bswap_v7i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev16 v0.16b, v0.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <7 x i16> @llvm.bswap.v7i16(<7 x i16> %a)
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ret <7 x i16> %res
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}
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declare <7 x i16> @llvm.bswap.v7i16(<7 x i16>)
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define <3 x i32> @bswap_v3i32(<3 x i32> %a){
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; CHECK-LABEL: bswap_v3i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev32 v0.16b, v0.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <3 x i32> @llvm.bswap.v3i32(<3 x i32> %a)
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ret <3 x i32> %res
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}
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declare <3 x i32> @llvm.bswap.v3i32(<3 x i32>)
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