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clang-p2996/llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
Momchil Velikov 2b3266c170 [AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11) (#116259) 
SVE2.2 introduces instructions with predicated forms with zeroing of the
inactive lanes. This allows in some cases to save a `movprfx` or a `mov`
instruction when emitting code for `_x` or `_z` variants of intrinsics.

This patch adds support for emitting the zeroing forms of `ABS`, `NEG`,
`FABS`, and `FNEG` instructions.
2024-11-29 14:53:15 +00:00

667 lines
24 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve < %s | FileCheck %s
; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2
target triple = "aarch64-linux"
define <vscale x 2 x double> @test_svabs_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svabs_f64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fabs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.d, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 2 x double> @test_svabs_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svabs_f64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fabs z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 2 x double> @test_svabs_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svabs_f64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: fabs z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 4 x float> @test_svabs_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svabs_f32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fabs z0.s, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.s, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 4 x float> @test_svabs_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svabs_f32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fabs z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 4 x float> @test_svabs_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svabs_f32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: fabs z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 8 x half> @test_svabs_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svabs_f16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fabs z0.h, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.h, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 8 x half> @test_svabs_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svabs_f16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fabs z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 8 x half> @test_svabs_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svabs_f16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #0 // =0x0
; CHECK-NEXT: fabs z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_f16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fabs z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 16 x i8> @test_svabs_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svabs_s8_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: abs z0.b, p0/m, z0.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s8_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.b, p0/z, z0.b
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %0
}
define <vscale x 16 x i8> @test_svabs_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svabs_s8_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: abs z0.b, p0/m, z1.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s8_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.b, p0/z, z1.b
; CHECK-2p2-NEXT: ret
entry:
%1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svabs_s8_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.b, #0 // =0x0
; CHECK-NEXT: abs z0.b, p0/m, z1.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s8_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.b, p0/z, z1.b
; CHECK-2p2-NEXT: ret
entry:
%1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %1
}
define <vscale x 8 x i16> @test_svabs_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svabs_s16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: abs z0.h, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.h, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 8 x i16> @test_svabs_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svabs_s16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: abs z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svabs_s16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #0 // =0x0
; CHECK-NEXT: abs z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 4 x i32> @test_svabs_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svabs_s32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.s, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 4 x i32> @test_svabs_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svabs_s32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: abs z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svabs_s32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: abs z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 2 x i64> @test_svabs_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svabs_s64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: abs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.d, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
define <vscale x 2 x i64> @test_svabs_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svabs_s64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: abs z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
define <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svabs_s64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: abs z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svabs_s64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: abs z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
define <vscale x 2 x double> @test_svneg_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svneg_f64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fneg z0.d, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.d, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fneg.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 2 x double> @test_svneg_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svneg_f64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fneg z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fneg.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 2 x double> @test_svneg_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svneg_f64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: fneg z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fneg.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 2 x double> %0
}
define <vscale x 4 x float> @test_svneg_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svneg_f32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fneg z0.s, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.s, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 4 x float> @test_svneg_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svneg_f32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fneg z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 4 x float> @test_svneg_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svneg_f32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: fneg z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 4 x float> %0
}
define <vscale x 8 x half> @test_svneg_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svneg_f16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fneg z0.h, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.h, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fneg.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 8 x half> @test_svneg_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svneg_f16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fneg z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fneg.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 8 x half> @test_svneg_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svneg_f16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #0 // =0x0
; CHECK-NEXT: fneg z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_f16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fneg z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fneg.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 8 x half> %0
}
define <vscale x 16 x i8> @test_svneg_s8_x_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svneg_s8_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: neg z0.b, p0/m, z0.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s8_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.b, p0/z, z0.b
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %0
}
define <vscale x 16 x i8> @test_svneg_s8_x_2(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svneg_s8_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: neg z0.b, p0/m, z1.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s8_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.b, p0/z, z1.b
; CHECK-2p2-NEXT: ret
entry:
%1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, double %z0, <vscale x 16 x i8> %x) {
; CHECK-LABEL: test_svneg_s8_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.b, #0 // =0x0
; CHECK-NEXT: neg z0.b, p0/m, z1.b
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s8_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.b, p0/z, z1.b
; CHECK-2p2-NEXT: ret
entry:
%1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %x)
ret <vscale x 16 x i8> %1
}
define <vscale x 8 x i16> @test_svneg_s16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svneg_s16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: neg z0.h, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.h, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 8 x i16> @test_svneg_s16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svneg_s16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: neg z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x i16> %x) {
; CHECK-LABEL: test_svneg_s16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #0 // =0x0
; CHECK-NEXT: neg z0.h, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.h, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %x)
ret <vscale x 8 x i16> %0
}
define <vscale x 4 x i32> @test_svneg_s32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svneg_s32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: neg z0.s, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.s, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 4 x i32> @test_svneg_s32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svneg_s32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: neg z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x i32> %x) {
; CHECK-LABEL: test_svneg_s32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: neg z0.s, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.s, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %x)
ret <vscale x 4 x i32> %0
}
define <vscale x 2 x i64> @test_svneg_s64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svneg_s64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: neg z0.d, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.d, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
define <vscale x 2 x i64> @test_svneg_s64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svneg_s64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: neg z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
define <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x i64> %x) {
; CHECK-LABEL: test_svneg_s64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: neg z0.d, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svneg_s64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: neg z0.d, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %x)
ret <vscale x 2 x i64> %0
}
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