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clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
Craig Topper 17f3e00911 Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)" 
The increase in fallbacks that was previously reported were not caused
by this change.

Original description:

This matches InstCombine and DAGCombine.

RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.

Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
2024-11-08 10:21:46 -08:00

5296 lines
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
define float @v_fdiv_f32(float %a, float %b) {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv float %a, %b
ret float %fdiv
}
define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #0 {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv float %a, %b
ret float %fdiv
}
define float @v_fdiv_f32_afn(float %a, float %b) {
; GCN-LABEL: v_fdiv_f32_afn:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_afn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_afn:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn float %a, %b
ret float %fdiv
}
define float @v_fdiv_f32_ulp25(float %a, float %b) {
; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_mov_b32_e32 v2, 0x6f800000
; GCN-FLUSH-NEXT: v_mov_b32_e32 v3, 0x2f800000
; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, v2
; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv float %a, %b, !fpmath !0
ret float %fdiv
}
define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX7-NEXT: v_rcp_f32_e32 v2, v2
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_25ulp:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, %y, !fpmath !0
ret float %div
}
define float @v_rcp_f32(float %x) {
; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_f32:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v3, v1
; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_rcp_f32:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v3, v1
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_f32:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_f32:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_f32:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2
; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_f32:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv float 1.0, %x
ret float %fdiv
}
define float @v_rcp_f32_arcp(float %x) {
; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32_arcp:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32_arcp:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32_arcp:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32_arcp:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_f32_arcp:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v3, v1
; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_rcp_f32_arcp:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v3, v1
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_f32_arcp:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_f32_arcp:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2
; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_f32_arcp:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp float 1.0, %x
ret float %fdiv
}
define float @v_rcp_f32_arcp_afn(float %x) {
; GCN-LABEL: v_rcp_f32_arcp_afn:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_rcp_f32_arcp_afn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_rcp_f32_arcp_afn:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp afn float 1.0, %x
ret float %fdiv
}
define float @v_rcp_f32_ulp25(float %x) {
; GFX6-IEEE-LABEL: v_rcp_f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v1, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_rcp_f32_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_f32_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_f32_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_f32_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_f32_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv float 1.0, %x, !fpmath !0
ret float %fdiv
}
define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {
; GCN-LABEL: v_fdiv_f32_afn_ulp25:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_afn_ulp25:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_afn_ulp25:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn float %a, %b, !fpmath !0
ret float %fdiv
}
define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v1
; GFX6-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v2, v1
; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v2, v1
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp float %a, %b, !fpmath !0
ret float %fdiv
}
define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_v2f32:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_v2f32:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v8, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v9, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v4, v8, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v8, v8
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v5, v9, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v9, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v10, v6, v8
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v11, v7, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v12, -v4, v10, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v13, -v5, v11, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, v12, v8, v10
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, v13, v9, v11
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v10, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v11, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v8, v10
; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v5, v5, v9, v11
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_v2f32:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v4
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v4, v6, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, v7, v6, v6
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v7, v5, v6
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v8, -v4, v7, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, v8, v6, v7
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v7, v5
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v1
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v5, v7, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v7, v7
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v6, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v5, v4, v6
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v7, v2, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v4, v6
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v5, v2, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_v2f32:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX89-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v9, v5
; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v8, v8
; GFX89-IEEE-NEXT: v_fma_f32 v11, -v5, v9, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v9, v9
; GFX89-IEEE-NEXT: v_mul_f32_e32 v10, v6, v8
; GFX89-IEEE-NEXT: v_mul_f32_e32 v11, v7, v9
; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6
; GFX89-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v7
; GFX89-IEEE-NEXT: v_fma_f32 v10, v12, v8, v10
; GFX89-IEEE-NEXT: v_fma_f32 v11, v13, v9, v11
; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v7
; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10
; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]
; GFX89-IEEE-NEXT: v_div_fmas_f32 v5, v5, v9, v11
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_v2f32:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v6, v4
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v4, v6, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v6, v7, v6, v6
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v7, v5, v6
; GFX89-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v7, v8, v6, v7
; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v5
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; GFX89-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v1
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v7, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v5, v7, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v7, v7
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v5, v4, v6
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v7, v2, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v5, v4, v6
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v5, v2, v4
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_v2f32:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v1
; GFX10-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v5
; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v8, v6
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, s4, v1, v3, v1
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v9, v7
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v10, v6
; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v8, v7
; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v8
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v7
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v8
; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v11
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, s4, v3, v3, v1
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v6
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v1
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v2
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v5
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_v2f32:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v1
; GFX11-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v7, v5
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
; GFX11-IEEE-NEXT: v_div_scale_f32 v8, s0, v1, v3, v1
; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v10, v6
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v11, v8, v7
; GFX11-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v8
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v6
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v7
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v8
; GFX11-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v11
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v1
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_v2f32:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
; GFX11-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v5
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v6, null, v3, v3, v1
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v6
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v5
; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v5
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v4
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x float> %a, %b
ret <2 x float> %fdiv
}
define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
; GCN-LABEL: v_fdiv_v2f32_afn:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_rcp_f32_e32 v3, v3
; GCN-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_v2f32_afn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_v2f32_afn:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x float> %a, %b
ret <2 x float> %fdiv
}
define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v6, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v5
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v6, v0, v6, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v3
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v6, v4
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v4, v0
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v1
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x6f800000
; GCN-FLUSH-NEXT: v_mov_b32_e32 v5, 0x2f800000
; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, v4
; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc
; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, v4
; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v5, vcc
; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v6
; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v6, v0
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v5
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v7, v1
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v1
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v2, v6, v2
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v3, v7, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v5
; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v0, v2
; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v1, v3
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v3
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v5
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v7, v1
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v1
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, v6, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, v7, v3
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v2|
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s0
; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v3|
; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v5
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x float> %a, %b, !fpmath !0
ret <2 x float> %fdiv
}
define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v8
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v8
; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_v2f32:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v6, v2
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v7, v3
; GFX89-IEEE-NEXT: v_fma_f32 v8, -v2, v6, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v6, v8, v6, v6
; GFX89-IEEE-NEXT: v_fma_f32 v9, -v3, v7, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v7, v9, v7, v7
; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v6
; GFX89-IEEE-NEXT: v_mul_f32_e32 v9, v5, v7
; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v4
; GFX89-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v5
; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v6, v8
; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v7, v9
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v4
; GFX89-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v5
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v6, v8
; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]
; GFX89-IEEE-NEXT: v_div_fmas_f32 v3, v3, v7, v9
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_rcp_v2f32:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v5, v5
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_v2f32:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_v2f32:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_v2f32:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
; GFX11-IEEE-NEXT: v_div_scale_f32 v6, s0, 1.0, v1, 1.0
; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX11-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_v2f32:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x
ret <2 x float> %fdiv
}
define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32_arcp:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32_arcp:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32_arcp:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v6
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v7
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v8
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v8
; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v9
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32_arcp:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v6, v2
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v7, v3
; GFX89-IEEE-NEXT: v_fma_f32 v8, -v2, v6, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v6, v8, v6, v6
; GFX89-IEEE-NEXT: v_fma_f32 v9, -v3, v7, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v7, v9, v7, v7
; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v6
; GFX89-IEEE-NEXT: v_mul_f32_e32 v9, v5, v7
; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v4
; GFX89-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v5
; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v6, v8
; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v7, v9
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v4
; GFX89-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v5
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v6, v8
; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]
; GFX89-IEEE-NEXT: v_div_fmas_f32 v3, v3, v7, v9
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_rcp_v2f32_arcp:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v5, v5
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.0
; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 0
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, 1.0
; GFX11-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
; GFX11-IEEE-NEXT: v_div_scale_f32 v6, s0, 1.0, v1, 1.0
; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v6, v5
; GFX11-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v8
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v6
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v5
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v8
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v6
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v9
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_v2f32_arcp:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x
ret <2 x float> %fdiv
}
define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) {
; GCN-LABEL: v_rcp_v2f32_arcp_afn:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_rcp_v2f32_arcp_afn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_rcp_v2f32_arcp_afn:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp afn <2 x float> <float 1.0, float 1.0>, %x
ret <2 x float> %fdiv
}
define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {
; GFX6-IEEE-LABEL: v_rcp_v2f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v1
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_rcp_v2f32_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_rcp_v2f32_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v3, v1
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_rcp_v2f32_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_rcp_v2f32_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v3, v1
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_rcp_v2f32_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x, !fpmath !0
ret <2 x float> %fdiv
}
define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {
; GCN-LABEL: v_fdiv_v2f32_afn_ulp25:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_rcp_f32_e32 v3, v3
; GCN-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_v2f32_afn_ulp25:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_v2f32_afn_ulp25:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x float> %a, %b, !fpmath !0
ret <2 x float> %fdiv
}
define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v2, vcc, 0, v2
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v2, v4, v2
; GFX6-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v3
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX6-IEEE-NEXT: v_sub_i32_e32 v3, vcc, 0, v3
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v2, v2, v3
; GFX6-IEEE-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v3
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v5
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v2, 0, v2
; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v3, 0, v3
; GFX10-IEEE-NEXT: v_ldexp_f32 v2, v4, v2
; GFX10-IEEE-NEXT: v_ldexp_f32 v3, v5, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v3
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v5
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, 0, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, 0, v3
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_ldexp_f32 v2, v4, v2
; GFX11-IEEE-NEXT: v_ldexp_f32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
ret <2 x float> %fdiv
}
define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) {
; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_rcp_f32_e32 v3, v3
; GCN-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-NEXT: v_mul_f32_e32 v1, v1, v3
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !0
ret <2 x float> %fdiv
}
define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX7-NEXT: v_rcp_f32_e32 v3, v2
; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX8-NEXT: v_rcp_f32_e32 v4, v2
; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv nnan ninf float %x, %y
ret float %div
}
define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX7-NEXT: v_rcp_f32_e32 v2, v2
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv nnan ninf float %x, %y, !fpmath !0
ret float %div
}
define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, float %y, float %z) #0 {
; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-NEXT: v_rcp_f32_e32 v3, v3
; GFX6-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v3, v0
; GFX6-NEXT: v_add_f32_e32 v0, v0, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX7-NEXT: v_rcp_f32_e32 v3, v3
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v3
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v4, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX8-NEXT: v_rcp_f32_e32 v3, v3
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v3
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v4, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v4
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v3
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v3, v0
; GFX6-IEEE-NEXT: v_add_f32_e32 v0, v0, v2
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v4
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v5, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v3, v0
; GFX6-FLUSH-NEXT: v_add_f32_e32 v0, v0, v2
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v3, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX10-NEXT: v_ldexp_f32 v0, v3, v0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv nnan ninf contract float %x, %y, !fpmath !0
%add = fadd contract float %div, %z
ret float %add
}
define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
; GFX7-NEXT: v_rcp_f32_e32 v3, v2
; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
; GFX8-NEXT: v_rcp_f32_e32 v4, v2
; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v2
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, v2
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v1, v1, v2
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, v2
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, null, v1, v1, v2
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_neglhs_f32_dynamic:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%neg.x = fneg float %x
%div = fdiv float %neg.x, %y
ret float %div
}
define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e64 v3, -v0
; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX7-NEXT: v_rcp_f32_e32 v2, v2
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX7-NEXT: v_frexp_mant_f32_e64 v0, -v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX8-NEXT: v_frexp_mant_f32_e64 v0, -v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e64 v4, -v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e64 v4, -v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e64 v3, -v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e64 v3, -v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%neg.x = fneg float %x
%div = fdiv float %neg.x, %y, !fpmath !0
ret float %div
}
define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
; GFX7-NEXT: v_rcp_f32_e32 v3, v2
; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
; GFX8-NEXT: v_rcp_f32_e32 v4, v2
; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v2, v2, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v2, v2, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v2, v2, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, null, v2, v2, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_negrhs_f32_dynamic:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%neg.y = fneg float %y
%div = fdiv float %x, %neg.y
ret float %div
}
define float @v_fdiv_f32_constrhs0_dynamic(float %x) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
; GFX7-NEXT: v_rcp_f32_e32 v2, v1
; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
; GFX8-NEXT: v_rcp_f32_e32 v3, v1
; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_constrhs0_dynamic:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, 12345.0
ret float %div
}
define float @v_fdiv_f32_constrhs0_dynamic_25ulp(float %x) #0 {
; GFX6-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e400
; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, 0x3fa9e0f0, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, 0x3fa9e0f0, v0
; GFX7-NEXT: v_add_i32_e32 v1, vcc, -14, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x3fa9e0f0, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, -14, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, 0x3f40e400
; GFX6-IEEE-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e400
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, 0x3f40e400
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e400
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_rcp_f32_e32 v1, 0x3f40e400
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_add_nc_u32_e32 v0, -14, v0
; GFX10-NEXT: v_mul_f32_e32 v1, v2, v1
; GFX10-NEXT: v_ldexp_f32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v1, 0x3f40e400
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_dual_mul_f32 v1, v2, v1 :: v_dual_add_nc_u32 v0, -14, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, 12345.0, !fpmath !0
ret float %div
}
define float @v_fdiv_f32_constlhs0_dynamic(float %x) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
; GFX7-NEXT: v_rcp_f32_e32 v2, v1
; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
; GFX8-NEXT: v_rcp_f32_e32 v3, v1
; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v1
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v1
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v1
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_mov_b32_e32 v1, 0x4640e400
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v1
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
; GFX11-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_constlhs0_dynamic:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float 12345.0, %x
ret float %div
}
define float @v_fdiv_f32_constlhs0_dynamic_25ulp(float %x) #0 {
; GFX6-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; GFX6-NEXT: v_rcp_f32_e32 v1, v1
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e400
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX7-NEXT: v_rcp_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, 14, v0
; GFX7-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX8-NEXT: v_rcp_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 14, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX8-NEXT: v_ldexp_f32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e400
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v1, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e400
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v1, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v1, v1
; GFX10-NEXT: v_sub_nc_u32_e32 v0, 14, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX10-NEXT: v_ldexp_f32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: v_sub_nc_u32_e32 v0, 14, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float 12345.0, %x, !fpmath !0
ret float %div
}
define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX7-NEXT: v_rcp_f32_e32 v3, v2
; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX8-NEXT: v_rcp_f32_e32 v4, v2
; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, %y
ret float %div
}
define float @v_fdiv_f32_dynamic_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {
; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX7-NEXT: v_rcp_f32_e32 v2, v2
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, %y, !fpmath !0
ret float %div
}
define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {
; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-FASTFMA: ; %bb.0:
; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-SLOWFMA: ; %bb.0:
; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX7-NEXT: v_rcp_f32_e32 v3, v2
; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX8-NEXT: v_rcp_f32_e32 v4, v2
; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-FLUSH-FASTFMA: ; %bb.0:
; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-IEEE-SLOWFMA: ; %bb.0:
; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX6-FLUSH-SLOWFMA: ; %bb.0:
; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX89-FLUSH: ; %bb.0:
; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3
; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3
; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX10-IEEE: ; %bb.0:
; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-IEEE-NEXT: s_denorm_mode 15
; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX10-FLUSH: ; %bb.0:
; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX10-FLUSH-NEXT: s_denorm_mode 3
; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX11-IEEE: ; %bb.0:
; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3
; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, %y
ret float %div
}
define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {
; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX7-NEXT: v_rcp_f32_e32 v2, v2
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_f32_e32 v2, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX10-NEXT: v_ldexp_f32 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
; EG: ; %bb.0:
; EG-NEXT: CF_END
; EG-NEXT: PAD
%div = fdiv float %x, %y, !fpmath !0
ret float %div
}
!0 = !{float 2.500000e+00}
attributes #0 = { "denormal-fp-math-f32"="dynamic,dynamic" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN-IEEE: {{.*}}
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