9ef1d37ffb
Similar to 806761a762
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.
126 lines
3.2 KiB
LLVM
126 lines
3.2 KiB
LLVM
; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
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; Tests atomic operations on AVR
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; CHECK-LABEL: atomic_load8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load8(ptr %foo) {
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%val = load atomic i8, ptr %foo unordered, align 1
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_swap8
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; CHECK: call __sync_lock_test_and_set_1
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define i8 @atomic_load_swap8(ptr %foo) {
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%val = atomicrmw xchg ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_cmp_swap8
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; CHECK: call __sync_val_compare_and_swap_1
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define i8 @atomic_load_cmp_swap8(ptr %foo) {
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%val = cmpxchg ptr %foo, i8 5, i8 10 acq_rel monotonic
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%value_loaded = extractvalue { i8, i1 } %val, 0
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ret i8 %value_loaded
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}
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; CHECK-LABEL: atomic_load_add8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: add [[RR1:r[0-9]+]], [[RD]]
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; CHECK-NEXT: st [[RR]], [[RR1]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_add8(ptr %foo) {
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%val = atomicrmw add ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_sub8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: mov [[TMP:r[0-9]+]], [[RD]]
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; CHECK-NEXT: sub [[TMP]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[TMP]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_sub8(ptr %foo) {
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%val = atomicrmw sub ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_and8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: and [[RR1:r[0-9]+]], [[RD]]
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; CHECK-NEXT: st [[RR]], [[RR1]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_and8(ptr %foo) {
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%val = atomicrmw and ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_or8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: or [[RR1:r[0-9]+]], [[RD]]
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; CHECK-NEXT: st [[RR]], [[RR1]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_or8(ptr %foo) {
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%val = atomicrmw or ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_xor8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: eor [[RR1:r[0-9]+]], [[RD]]
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; CHECK-NEXT: st [[RR]], [[RR1]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_xor8(ptr %foo) {
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%val = atomicrmw xor ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_nand8
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; CHECK: call __sync_fetch_and_nand_1
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define i8 @atomic_load_nand8(ptr %foo) {
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%val = atomicrmw nand ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_max8
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; CHECK: call __sync_fetch_and_max_1
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define i8 @atomic_load_max8(ptr %foo) {
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%val = atomicrmw max ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_min8
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; CHECK: call __sync_fetch_and_min_1
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define i8 @atomic_load_min8(ptr %foo) {
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%val = atomicrmw min ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_umax8
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; CHECK: call __sync_fetch_and_umax_1
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define i8 @atomic_load_umax8(ptr %foo) {
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%val = atomicrmw umax ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_umin8
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; CHECK: call __sync_fetch_and_umin_1
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define i8 @atomic_load_umin8(ptr %foo) {
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%val = atomicrmw umin ptr %foo, i8 13 seq_cst
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ret i8 %val
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}
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