9122c5235e
This is based on other targets like PPC/AArch64 and some experiments. This PR will only enable bidirectional scheduling and tracking register pressure. Disclaimer: I haven't tested it on many cores, maybe we should make some options being features. I believe downstreams must have tried this before, so feedbacks are welcome.
29 lines
903 B
LLVM
29 lines
903 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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define i16 @narrow_load(ptr %p1, ptr %p2) {
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; CHECK-LABEL: narrow_load:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lhu a2, 0(a0)
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; CHECK-NEXT: lui a3, 2
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; CHECK-NEXT: lui a4, 16
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; CHECK-NEXT: addiw a3, a3, -1
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; CHECK-NEXT: addi a4, a4, -1
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; CHECK-NEXT: xor a2, a2, a3
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; CHECK-NEXT: xor a4, a3, a4
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; CHECK-NEXT: or a2, a2, a4
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; CHECK-NEXT: sw a2, 0(a1)
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; CHECK-NEXT: lhu a0, 0(a0)
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; CHECK-NEXT: and a0, a0, a3
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; CHECK-NEXT: ret
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entry:
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%bf.load = load i16, ptr %p1, align 2
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%bf.clear = and i16 %bf.load, 8191
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%not = xor i16 %bf.clear, -1
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%conv1 = zext i16 %not to i32
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store i32 %conv1, ptr %p2, align 4
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%bf.load2 = load i16, ptr %p1, align 2
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%bf.clear3 = and i16 %bf.load2, 8191
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ret i16 %bf.clear3
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}
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