6caf9f8236
As noted on #117557 - its not worth performing scalar float fabs/fneg on the fpu if we're not doing any other fp ops. This is currently limited to store + load pairs - I could try to extend this further if necessary, but we need to be careful that we don't end up in an infinite loop with the DAGCombiner foldBitcastedFPLogic combine. Fixes #117557
28 lines
987 B
LLVM
28 lines
987 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -enable-unsafe-fp-math | FileCheck %s
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; Don't fold the incoming stack arguments into the xorps instructions used
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; to do floating-point negations, because the arguments aren't vectors
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; and aren't vector-aligned.
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define void @foo(ptr %p, ptr %q, float %s, float %y) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $-2147483648, %edx # imm = 0x80000000
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: xorl %edx, %esi
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; CHECK-NEXT: movl %esi, (%ecx)
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; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl %edx, (%eax)
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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%ss = fsub float -0.0, %s
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%yy = fsub float -0.0, %y
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store float %ss, ptr %p
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store float %yy, ptr %q
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ret void
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}
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