f673882323
Currently targets without LZCNT/TZCNT won't speculate with BSR/BSF instructions in case they have a zero value input, meaning we always insert a test+branch for the zero-input case. This patch proposes we allow speculation if the target has CMOV, and perform a branchless select instead to handle the zero input case. This will predominately help x86-64 targets where we haven't set any particular cpu target. We already always perform BSR/BSF instructions if we were lowering a CTLZ/CTTZ_ZERO_UNDEF instruction.
73 lines
2.8 KiB
LLVM
73 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes="require<profile-summary>,function(codegenprepare)" < %s | FileCheck %s --check-prefix=SLOW
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; RUN: opt -S -passes="require<profile-summary>,function(codegenprepare)" -mattr=+bmi < %s | FileCheck %s --check-prefix=FAST_TZ
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; RUN: opt -S -passes="require<profile-summary>,function(codegenprepare)" -mattr=+lzcnt < %s | FileCheck %s --check-prefix=FAST_LZ
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; RUN: opt -S -enable-debugify -passes="require<profile-summary>,function(codegenprepare)" < %s | FileCheck %s --check-prefix=DEBUGINFO
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; RUN: opt -S -enable-debugify -passes="require<profile-summary>,function(codegenprepare)" --try-experimental-debuginfo-iterators < %s | FileCheck %s --check-prefix=DEBUGINFO
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target triple = "x86_64-unknown-unknown"
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target datalayout = "e-n32:64"
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; If the intrinsic is cheap, nothing should change.
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; If the intrinsic is expensive, check if the input is zero to avoid the call.
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; This is undoing speculation that may have been created by SimplifyCFG + InstCombine.
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define i64 @cttz(i64 %A) {
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; SLOW-LABEL: @cttz(
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; SLOW-NEXT: entry:
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; SLOW-NEXT: [[Z:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
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; SLOW-NEXT: ret i64 [[Z]]
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;
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; FAST_TZ-LABEL: @cttz(
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; FAST_TZ-NEXT: entry:
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; FAST_TZ-NEXT: [[Z:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
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; FAST_TZ-NEXT: ret i64 [[Z]]
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;
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; FAST_LZ-LABEL: @cttz(
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; FAST_LZ-NEXT: entry:
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; FAST_LZ-NEXT: [[Z:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
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; FAST_LZ-NEXT: ret i64 [[Z]]
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;
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; DEBUGINFO-LABEL: @cttz(
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; DEBUGINFO-NEXT: entry:
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; DEBUGINFO-NEXT: [[Z:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false), !dbg [[DBG11:![0-9]+]]
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; DEBUGINFO-NEXT: #dbg_value(i64 [[Z]], [[META9:![0-9]+]], !DIExpression(), [[DBG11]])
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; DEBUGINFO-NEXT: ret i64 [[Z]], !dbg [[DBG12:![0-9]+]]
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;
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entry:
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%z = call i64 @llvm.cttz.i64(i64 %A, i1 false)
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ret i64 %z
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}
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define i64 @ctlz(i64 %A) {
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; SLOW-LABEL: @ctlz(
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; SLOW-NEXT: entry:
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; SLOW-NEXT: [[Z:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
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; SLOW-NEXT: ret i64 [[Z]]
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;
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; FAST_TZ-LABEL: @ctlz(
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; FAST_TZ-NEXT: entry:
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; FAST_TZ-NEXT: [[Z:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
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; FAST_TZ-NEXT: ret i64 [[Z]]
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;
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; FAST_LZ-LABEL: @ctlz(
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; FAST_LZ-NEXT: entry:
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; FAST_LZ-NEXT: [[Z:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
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; FAST_LZ-NEXT: ret i64 [[Z]]
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;
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; DEBUGINFO-LABEL: @ctlz(
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; DEBUGINFO-NEXT: entry:
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; DEBUGINFO-NEXT: [[Z:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false), !dbg [[DBG16:![0-9]+]]
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; DEBUGINFO-NEXT: #dbg_value(i64 [[Z]], [[META15:![0-9]+]], !DIExpression(), [[DBG16]])
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; DEBUGINFO-NEXT: ret i64 [[Z]], !dbg [[DBG17:![0-9]+]]
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;
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entry:
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%z = call i64 @llvm.ctlz.i64(i64 %A, i1 false)
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ret i64 %z
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}
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i64 @llvm.ctlz.i64(i64, i1)
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