fe04290482
Most AArch64 cpus outside of Neoverse V1 (256) and A64FX (512) have an SVE vector length of 128, and in environments like Android (where no mcpu option is common) we would expect all cpus to match. This patch changes the default vector length to 128 with -mcpu=generic, to match the most common case.
57 lines
2.3 KiB
LLVM
57 lines
2.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -mtriple=aarch64 -mattr=+sve \
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; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
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; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
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; RUN: opt -mtriple=aarch64 -mattr=+sve -mcpu=generic \
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; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
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; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
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; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v1 \
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; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
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; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING2
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; RUN: opt -mtriple=aarch64 -mcpu=neoverse-n2 \
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; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
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; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
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; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v2 \
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; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
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; RUN: | FileCheck %s --check-prefixes=NEOVERSEV2
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; VSCALEFORTUNING1: Cost for VF vscale x 2: 11 (Estimated cost per lane: 5.
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; VSCALEFORTUNING1: Cost for VF vscale x 4: 11 (Estimated cost per lane: 2.
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; VSCALEFORTUNING1: LV: Selecting VF: vscale x 16
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; VSCALEFORTUNING2: Cost for VF vscale x 2: 11 (Estimated cost per lane: 2.
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; VSCALEFORTUNING2: Cost for VF vscale x 4: 11 (Estimated cost per lane: 1.
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; VSCALEFORTUNING2: LV: Selecting VF: vscale x 16
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; NEOVERSEV2: Cost for VF vscale x 2: 11 (Estimated cost per lane: 5.
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; NEOVERSEV2: Cost for VF vscale x 4: 11 (Estimated cost per lane: 2.
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; NEOVERSEV2: LV: Selecting VF: 16
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; VSCALEFORTUNING1: <vscale x 16 x i8>
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; VSCALEFORTUNING2: <vscale x 16 x i8>
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; NEOVERSEV2: <16 x i8>
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define void @test0(ptr %a, ptr %b, ptr %c) #0 {
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%arrayidx = getelementptr inbounds i8, ptr %c, i64 %iv
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%0 = load i8, ptr %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %iv
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%1 = load i8, ptr %arrayidx2, align 4
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%add = add nsw i8 %0, %1
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%arrayidx5 = getelementptr inbounds i8, ptr %a, i64 %iv
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store i8 %add, ptr %arrayidx5, align 4
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, 1024
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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ret void
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}
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