94df95de6b
SK_PermuteTwoSrc legalization has to assume any of the legalised source registers could be referenced in split shuffles, but if we already know that each 128-bit lane only references elements from the same lane of the source operands, then this scaling won't occur. Hopefully this can help with #113356 without us having to get full processShuffleMasks canonicalization finished first.
37 lines
2.2 KiB
LLVM
37 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -O3 -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -O3 -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -O3 -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -O3 -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -passes="default<O3>" -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes="default<O3>" -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -passes="default<O3>" -S < %s | FileCheck %s
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; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes="default<O3>" -S < %s | FileCheck %s
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define <4 x double> @PR94546(<4 x double> %a, <4 x double> %b) {
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; CHECK-LABEL: @PR94546(
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <4 x i32> <i32 0, i32 poison, i32 poison, i32 6>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <4 x i32> <i32 1, i32 poison, i32 poison, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <4 x double> [[TMP3]]
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;
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%vecext = extractelement <4 x double> %a, i32 0
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%vecext1 = extractelement <4 x double> %a, i32 1
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%add = fadd double %vecext, %vecext1
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%vecinit = insertelement <4 x double> poison, double %add, i32 0
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%vecext2 = extractelement <4 x double> %a, i32 2
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%vecext3 = extractelement <4 x double> %a, i32 3
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%add4 = fadd double %vecext2, %vecext3
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%vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1
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%vecext6 = extractelement <4 x double> %b, i32 0
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%vecext7 = extractelement <4 x double> %b, i32 1
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%add8 = fadd double %vecext6, %vecext7
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%vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2
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%vecext10 = extractelement <4 x double> %b, i32 2
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%vecext11 = extractelement <4 x double> %b, i32 3
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%add12 = fadd double %vecext10, %vecext11
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%vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3
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%shuffle = shufflevector <4 x double> %vecinit13, <4 x double> %a, <4 x i32> <i32 0, i32 poison, i32 poison, i32 3>
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ret <4 x double> %shuffle
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}
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