After seeing the bug that #142185 fixed, I thought it might be a good idea to start verifying that nodes are formed correctly. This patch introduces the verifyTargetNode function and adds these opcodes. More opcodes can be added in later patches.
53 lines
2.0 KiB
C++
53 lines
2.0 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSelectionDAGInfo.h"
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#define GET_SDNODE_DESC
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#include "RISCVGenSDNodeInfo.inc"
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using namespace llvm;
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RISCVSelectionDAGInfo::RISCVSelectionDAGInfo()
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: SelectionDAGGenTargetInfo(RISCVGenSDNodeInfo) {}
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RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default;
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void RISCVSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const {
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#ifndef NDEBUG
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switch (N->getOpcode()) {
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default:
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return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
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case RISCVISD::VQDOT_VL:
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case RISCVISD::VQDOTU_VL:
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case RISCVISD::VQDOTSU_VL: {
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assert(N->getNumValues() == 1 && "Expected one result!");
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assert(N->getNumOperands() == 5 && "Expected five operands!");
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EVT VT = N->getValueType(0);
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assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i32 &&
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"Expected result to be an i32 scalable vector");
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assert(N->getOperand(0).getValueType() == VT &&
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N->getOperand(1).getValueType() == VT &&
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N->getOperand(2).getValueType() == VT &&
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"Expected result and first 3 operands to have the same type!");
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EVT MaskVT = N->getOperand(3).getValueType();
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assert(MaskVT.isScalableVector() &&
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MaskVT.getVectorElementType() == MVT::i1 &&
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MaskVT.getVectorElementCount() == VT.getVectorElementCount() &&
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"Expected mask VT to be an i1 scalable vector with same number of "
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"elements as the result");
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assert((N->getOperand(4).getValueType() == MVT::i32 ||
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N->getOperand(4).getValueType() == MVT::i64) &&
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"Expect VL operand to be i32 or i64");
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break;
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}
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}
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#endif
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}
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