369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
65 lines
2.2 KiB
LLVM
65 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80 | FileCheck %s
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; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80 | %ptxas-verify -arch=sm_90 %}
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target triple = "nvptx64-nvidia-cuda"
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declare {i32, i1} @llvm.nvvm.elect.sync(i32)
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define {i32, i1} @elect_sync(i32 %mask) {
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; CHECK-LABEL: elect_sync(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<2>;
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; CHECK-NEXT: .reg .b16 %rs<2>;
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [elect_sync_param_0];
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; CHECK-NEXT: elect.sync %r2|%p1, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: selp.b16 %rs1, -1, 0, %p1;
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; CHECK-NEXT: st.param.b8 [func_retval0+4], %rs1;
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; CHECK-NEXT: ret;
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%val = call {i32, i1} @llvm.nvvm.elect.sync(i32 %mask)
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ret {i32, i1} %val
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}
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define {i32, i1} @elect_sync_imm() {
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; CHECK-LABEL: elect_sync_imm(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<2>;
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; CHECK-NEXT: .reg .b16 %rs<2>;
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: elect.sync %r1|%p1, -1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: selp.b16 %rs1, -1, 0, %p1;
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; CHECK-NEXT: st.param.b8 [func_retval0+4], %rs1;
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; CHECK-NEXT: ret;
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%val = call {i32, i1} @llvm.nvvm.elect.sync(i32 u0xffffffff)
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ret {i32, i1} %val
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}
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; When there are two elect.sync's make sure that
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; the second one is not optimized away.
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define {i32, i1} @elect_sync_twice(i32 %mask) {
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; CHECK-LABEL: elect_sync_twice(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<3>;
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; CHECK-NEXT: .reg .b16 %rs<2>;
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [elect_sync_twice_param_0];
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; CHECK-NEXT: elect.sync %r2|%p1, %r1;
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; CHECK-NEXT: elect.sync %r3|%p2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: selp.b16 %rs1, -1, 0, %p1;
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; CHECK-NEXT: st.param.b8 [func_retval0+4], %rs1;
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; CHECK-NEXT: ret;
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%val = call {i32, i1} @llvm.nvvm.elect.sync(i32 %mask)
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%val2 = call {i32, i1} @llvm.nvvm.elect.sync(i32 %mask)
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ret {i32, i1} %val
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}
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