caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6a21dfaac66ffa39dc7faaec1cd7932099c052d4
clang-p2996/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
Alex Bradbury 3d2650bdeb [RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663) 
The logic in RISCVMatInt would previously produce lui+addiw on RV64
whenever a 32-bit integer must be materialised and the Hi20 and Lo12
parts are non-zero. However, sometimes addi can be used equivalently
(whenever the sign extension behaviour of addiw would be a no-op). This
patch moves to using addiw only when necessary. Although there is
absolutely no advantage in terms of compressibility or performance, this
has the following advantages:
* It's more consistent with logic used elsewhere in the backend. For
instance, RISCVOptWInstrs will try to convert addiw to addi on the basis
it reduces test diffs vs RV32.
* This matches the lowering GCC does in its codegen path. Unlike LLVM,
GCC seems to have different expansion logic for the assembler vs
codegen. For codegen it will use lui+addi if possible, but expanding
`li` in the assembler will always produces lui+addiw as LLVM did prior
to this commit. As someone who has been looking at a lot of gcc vs clang
diffs lately, reducing unnecessary divergence is of at least some value.
* As the diff for fold-mem-offset.ll shows, we can fold memory offsets
in more cases when addi is used. Memory offset folding could be taught
to recognise when the addiw could be replaced with an addi, but that
seems unnecessary when we can simply change the logic in RISCVMatInt.

As pointed out by @topperc during review, making this change without
modifying RISCVOptWInstrs risks introducing some cases where we fail to
remove a sext.w that we removed before. I've incorporated a patch based
on a suggestion from Craig that avoids it, and also adds appropriate
RISCVOptWInstrs test cases.

The initial patch description noted that the main motivation was to
avoid unnecessary differences both for RV32/RV64 and when comparing GCC,
but noted that very occasionally we see a benefit from memory offset
folding kicking in when it didn't before. Looking at the dynamic
instruction count difference for SPEC benchmarks targeting rva22u64 and
it shows we actually get a meaningful
~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data
more closely, the codegen difference is in `LBM_performStreamCollideTRT`
which as a function accounts for ~98% for dynamically executed
instructions and the codegen diffs appear to be a knock-on effect of the
address merging reducing register pressure right from function entry
(for instance, we get a big reduction in dynamically executed loads in
that function).

Below is the icount data (rva22u64 -O3, no LTO):
```
Benchmark                Baseline            This PR   Diff (%)
============================================================
500.perlbench_r         174116601991    174115795810     -0.00%
502.gcc_r               218903280858    218903215788     -0.00%
505.mcf_r               131208029185    131207692803     -0.00%
508.namd_r              217497594322    217497594297     -0.00%
510.parest_r            289314486153    289313577652     -0.00%
511.povray_r             30640531048     30640765701      0.00%
519.lbm_r                95897914862     91712688050     -4.36%
520.omnetpp_r           134641549722    134867015683      0.17%
523.xalancbmk_r         281462762992    281432092673     -0.01%
525.x264_r              379776121941    379535558210     -0.06%
526.blender_r           659736022025    659738387343      0.00%
531.deepsjeng_r         349122867552    349122867481     -0.00%
538.imagick_r           238558760552    238558753269     -0.00%
541.leela_r             406578560612    406385135260     -0.05%
544.nab_r               400997131674    400996765827     -0.00%
557.xz_r                130079522194    129945515709     -0.10%

```

The instcounting setup I use doesn't have good support for drilling down
into functions from outside the linked executable (e.g. libc). The
difference in omnetpp all seems to come from there, and does not reflect
any degradation in codegen quality.

I can confirm with the current version of the PR there is no change in
the number of static sext.w across all the SPEC 2017 benchmarks
(rva22u64 O3)

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-06-02 22:24:50 +01:00

1742 lines
52 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32ZB,RV32ZBB
; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZB,RV64ZBB
; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32ZB,RV32ZBKB
; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZB,RV64ZBKB
declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
declare i8 @llvm.bitreverse.i8(i8)
declare i16 @llvm.bitreverse.i16(i16)
declare i32 @llvm.bitreverse.i32(i32)
declare i64 @llvm.bitreverse.i64(i64)
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZB-LABEL: test_bswap_i16:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: srli a0, a0, 16
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_i16:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp
}
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV32ZB-LABEL: test_bswap_i32:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_i32:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
}
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: or a4, a5, a4
; RV32I-NEXT: slli a5, a1, 24
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: or a3, a0, a3
; RV32I-NEXT: or a0, a1, a2
; RV32I-NEXT: or a1, a3, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: srliw a3, a3, 24
; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a4, a5, a4
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV32ZB-LABEL: test_bswap_i64:
; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a2, a1
; RV32ZB-NEXT: rev8 a1, a0
; RV32ZB-NEXT: mv a0, a2
; RV32ZB-NEXT: ret
;
; RV64ZB-LABEL: test_bswap_i64:
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp
}
define i7 @test_bitreverse_i7(i7 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i7:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a3, 344064
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 348160
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a0, a0, 25
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_i7:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: srli a6, a0, 8
; RV64I-NEXT: srliw a7, a0, 24
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: srliw a6, a6, 24
; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: or a4, a6, a4
; RV64I-NEXT: lui a6, 209715
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: slli a7, a7, 32
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a6, a6, 819
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a5, a5, a7
; RV64I-NEXT: slli a7, a3, 32
; RV64I-NEXT: add a3, a3, a7
; RV64I-NEXT: slli a7, a6, 32
; RV64I-NEXT: add a6, a6, a7
; RV64I-NEXT: or a1, a4, a1
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: li a2, 21
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: li a4, 85
; RV64I-NEXT: slli a2, a2, 58
; RV64I-NEXT: slli a4, a4, 56
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a6
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a0, a0, 57
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_i7:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: lui a1, 61681
; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: addi a1, a1, -241
; RV32ZBB-NEXT: and a2, a2, a1
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: lui a1, 209715
; RV32ZBB-NEXT: addi a1, a1, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: srli a2, a0, 2
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: and a1, a2, a1
; RV32ZBB-NEXT: lui a2, 344064
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: lui a1, 348160
; RV32ZBB-NEXT: and a1, a0, a1
; RV32ZBB-NEXT: srli a0, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: srli a0, a0, 25
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_i7:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a3, a1, 32
; RV64ZBB-NEXT: add a1, a1, a3
; RV64ZBB-NEXT: slli a3, a2, 32
; RV64ZBB-NEXT: add a2, a2, a3
; RV64ZBB-NEXT: srli a3, a0, 4
; RV64ZBB-NEXT: and a3, a3, a1
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: li a1, 21
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a3, a0
; RV64ZBB-NEXT: srli a3, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a2, a3, a2
; RV64ZBB-NEXT: li a3, 85
; RV64ZBB-NEXT: slli a1, a1, 58
; RV64ZBB-NEXT: slli a3, a3, 56
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a2, a0
; RV64ZBB-NEXT: srli a2, a0, 1
; RV64ZBB-NEXT: and a0, a0, a3
; RV64ZBB-NEXT: and a1, a2, a1
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a0, a0, 57
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_i7:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: slli a0, a0, 24
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 25
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i7:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: slli a0, a0, 56
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 57
; RV64ZBKB-NEXT: ret
%tmp = call i7 @llvm.bitreverse.i7(i7 %a)
ret i7 %tmp
}
define i8 @test_bitreverse_i8(i8 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a1, a0, 15
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: srli a0, a0, 28
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: andi a1, a0, 51
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: andi a0, a0, 51
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: andi a1, a0, 85
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: andi a0, a0, 85
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a0, 15
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: srli a0, a0, 60
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a0, 51
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: andi a0, a0, 51
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a0, 85
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: andi a0, a0, 85
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_i8:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andi a1, a0, 15
; RV32ZBB-NEXT: slli a0, a0, 24
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: srli a0, a0, 28
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: andi a1, a0, 51
; RV32ZBB-NEXT: srli a0, a0, 2
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: andi a0, a0, 51
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: andi a1, a0, 85
; RV32ZBB-NEXT: srli a0, a0, 1
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: andi a0, a0, 85
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andi a1, a0, 15
; RV64ZBB-NEXT: slli a0, a0, 56
; RV64ZBB-NEXT: slli a1, a1, 4
; RV64ZBB-NEXT: srli a0, a0, 60
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: andi a1, a0, 51
; RV64ZBB-NEXT: srli a0, a0, 2
; RV64ZBB-NEXT: slli a1, a1, 2
; RV64ZBB-NEXT: andi a0, a0, 51
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: andi a1, a0, 85
; RV64ZBB-NEXT: srli a0, a0, 1
; RV64ZBB-NEXT: slli a1, a1, 1
; RV64ZBB-NEXT: andi a0, a0, 85
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_i8:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i8:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %tmp
}
define i16 @test_bitreverse_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 3
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_i16:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: lui a1, 15
; RV32ZBB-NEXT: srli a2, a0, 12
; RV32ZBB-NEXT: addi a1, a1, 240
; RV32ZBB-NEXT: and a1, a2, a1
; RV32ZBB-NEXT: lui a2, 3
; RV32ZBB-NEXT: srli a0, a0, 20
; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: andi a0, a0, -241
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: lui a2, 5
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 15
; RV64ZBB-NEXT: srli a2, a0, 44
; RV64ZBB-NEXT: addi a1, a1, 240
; RV64ZBB-NEXT: and a1, a2, a1
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: srli a0, a0, 52
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: andi a0, a0, -241
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_i16:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 16
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: ret
%tmp = call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %tmp
}
define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: lui a1, 61681
; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: addi a1, a1, -241
; RV32ZBB-NEXT: and a2, a2, a1
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: lui a1, 209715
; RV32ZBB-NEXT: addi a1, a1, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: srli a2, a0, 2
; RV32ZBB-NEXT: and a0, a0, a1
; RV32ZBB-NEXT: and a1, a2, a1
; RV32ZBB-NEXT: lui a2, 349525
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: srli a2, a0, 36
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: and a1, a2, a1
; RV64ZBB-NEXT: lui a2, 986895
; RV64ZBB-NEXT: srli a0, a0, 28
; RV64ZBB-NEXT: addi a2, a2, 240
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slliw a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: ret
%tmp = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %tmp
}
define i64 @test_bitreverse_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: slli a5, a1, 24
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: srli a7, a0, 8
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: and a7, a7, a3
; RV32I-NEXT: or a4, a7, a4
; RV32I-NEXT: lui a7, 209715
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: addi a7, a7, 819
; RV32I-NEXT: addi a5, a5, 1365
; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: srli a3, a0, 4
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: srli a3, a0, 2
; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: srli a3, a0, 1
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a4, a0, 1
; RV32I-NEXT: or a0, a2, a1
; RV32I-NEXT: or a1, a3, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: srli a6, a0, 8
; RV64I-NEXT: srliw a7, a0, 24
; RV64I-NEXT: lui t0, 61681
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: srliw a6, a6, 24
; RV64I-NEXT: slli a6, a6, 24
; RV64I-NEXT: or a4, a6, a4
; RV64I-NEXT: lui a6, 349525
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: slli a7, a7, 32
; RV64I-NEXT: addi t0, t0, -241
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: addi a6, a6, 1365
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a5, a5, a7
; RV64I-NEXT: slli a7, t0, 32
; RV64I-NEXT: add a7, t0, a7
; RV64I-NEXT: slli t0, a3, 32
; RV64I-NEXT: add a3, a3, t0
; RV64I-NEXT: slli t0, a6, 32
; RV64I-NEXT: add a6, a6, t0
; RV64I-NEXT: or a1, a4, a1
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a7
; RV64I-NEXT: and a1, a1, a7
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a6
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a1, a1
; RV32ZBB-NEXT: lui a2, 61681
; RV32ZBB-NEXT: lui a3, 209715
; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: srli a4, a1, 4
; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: srli a5, a0, 4
; RV32ZBB-NEXT: and a4, a4, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a5, a5, a2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: lui a2, 349525
; RV32ZBB-NEXT: addi a3, a3, 819
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a1, a4, a1
; RV32ZBB-NEXT: or a0, a5, a0
; RV32ZBB-NEXT: srli a4, a1, 2
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: srli a5, a0, 2
; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: and a4, a4, a3
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: and a3, a5, a3
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a1, a4, a1
; RV32ZBB-NEXT: or a0, a3, a0
; RV32ZBB-NEXT: srli a3, a1, 1
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: srli a4, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a3, a3, a2
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: and a2, a4, a2
; RV32ZBB-NEXT: slli a4, a0, 1
; RV32ZBB-NEXT: or a0, a3, a1
; RV32ZBB-NEXT: or a1, a2, a4
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32
; RV64ZBB-NEXT: add a2, a2, a4
; RV64ZBB-NEXT: slli a4, a3, 32
; RV64ZBB-NEXT: add a3, a3, a4
; RV64ZBB-NEXT: srli a4, a0, 4
; RV64ZBB-NEXT: and a4, a4, a1
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a4, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a3
; RV64ZBB-NEXT: and a1, a1, a3
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_i64:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a1, a1
; RV32ZBKB-NEXT: rev8 a2, a0
; RV32ZBKB-NEXT: brev8 a0, a1
; RV32ZBKB-NEXT: brev8 a1, a2
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %tmp
}
define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_bitreverse_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lui a2, 3
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_bitreverse_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bswap_bitreverse_i16:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: lui a2, 1
; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: lui a2, 3
; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: lui a2, 5
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bswap_bitreverse_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 1
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bswap_bitreverse_i16:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bswap_bitreverse_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
%tmp2 = call i16 @llvm.bitreverse.i16(i16 %tmp)
ret i16 %tmp2
}
define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_bitreverse_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_bitreverse_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bswap_bitreverse_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: lui a2, 61681
; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: lui a2, 209715
; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: lui a2, 349525
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bswap_bitreverse_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 61681
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slliw a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slliw a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bswap_bitreverse_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bswap_bitreverse_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
%tmp2 = call i32 @llvm.bitreverse.i32(i32 %tmp)
ret i32 %tmp2
}
define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_bitreverse_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: srli a5, a1, 4
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bswap_bitreverse_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slli a4, a1, 32
; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: slli a4, a2, 32
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: slli a4, a3, 32
; RV64I-NEXT: add a3, a3, a4
; RV64I-NEXT: srli a4, a0, 4
; RV64I-NEXT: and a4, a4, a1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a4, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bswap_bitreverse_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: lui a3, 61681
; RV32ZBB-NEXT: lui a4, 209715
; RV32ZBB-NEXT: srli a5, a1, 4
; RV32ZBB-NEXT: addi a3, a3, -241
; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: and a5, a5, a3
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: lui a3, 349525
; RV32ZBB-NEXT: addi a4, a4, 819
; RV32ZBB-NEXT: addi a3, a3, 1365
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a5, a1
; RV32ZBB-NEXT: srli a2, a0, 2
; RV32ZBB-NEXT: and a0, a0, a4
; RV32ZBB-NEXT: srli a5, a1, 2
; RV32ZBB-NEXT: and a1, a1, a4
; RV32ZBB-NEXT: and a2, a2, a4
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: and a4, a5, a4
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a4, a1
; RV32ZBB-NEXT: srli a2, a0, 1
; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: srli a4, a1, 1
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: and a3, a4, a3
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a3, a1
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bswap_bitreverse_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32
; RV64ZBB-NEXT: add a2, a2, a4
; RV64ZBB-NEXT: slli a4, a3, 32
; RV64ZBB-NEXT: add a3, a3, a4
; RV64ZBB-NEXT: srli a4, a0, 4
; RV64ZBB-NEXT: and a4, a4, a1
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a4, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a3
; RV64ZBB-NEXT: and a1, a1, a3
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bswap_bitreverse_i64:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: brev8 a1, a1
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bswap_bitreverse_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
%tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp)
ret i64 %tmp2
}
define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lui a2, 3
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_bswap_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_bswap_i16:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: lui a2, 1
; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: lui a2, 3
; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: lui a2, 5
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_bswap_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 1
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_bswap_i16:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_bswap_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i16 @llvm.bitreverse.i16(i16 %a)
%tmp2 = call i16 @llvm.bswap.i16(i16 %tmp)
ret i16 %tmp2
}
define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_bswap_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slliw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_bswap_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a1, a0, 4
; RV32ZBB-NEXT: lui a2, 61681
; RV32ZBB-NEXT: addi a2, a2, -241
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: lui a2, 209715
; RV32ZBB-NEXT: addi a2, a2, 819
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 2
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: lui a2, 349525
; RV32ZBB-NEXT: addi a2, a2, 1365
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: and a0, a0, a2
; RV32ZBB-NEXT: and a1, a1, a2
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_bswap_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 61681
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slliw a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slliw a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_bswap_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_bswap_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i32 @llvm.bitreverse.i32(i32 %a)
%tmp2 = call i32 @llvm.bswap.i32(i32 %tmp)
ret i32 %tmp2
}
define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bitreverse_bswap_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: lui a4, 209715
; RV32I-NEXT: srli a5, a1, 4
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a4, a4, 819
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: srli a2, a0, 2
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: and a4, a5, a4
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_bitreverse_bswap_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slli a4, a1, 32
; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: slli a4, a2, 32
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: slli a4, a3, 32
; RV64I-NEXT: add a3, a3, a4
; RV64I-NEXT: srli a4, a0, 4
; RV64I-NEXT: and a4, a4, a1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a4, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: test_bitreverse_bswap_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a2, a0, 4
; RV32ZBB-NEXT: lui a3, 61681
; RV32ZBB-NEXT: lui a4, 209715
; RV32ZBB-NEXT: srli a5, a1, 4
; RV32ZBB-NEXT: addi a3, a3, -241
; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: and a5, a5, a3
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: lui a3, 349525
; RV32ZBB-NEXT: addi a4, a4, 819
; RV32ZBB-NEXT: addi a3, a3, 1365
; RV32ZBB-NEXT: slli a0, a0, 4
; RV32ZBB-NEXT: slli a1, a1, 4
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a5, a1
; RV32ZBB-NEXT: srli a2, a0, 2
; RV32ZBB-NEXT: and a0, a0, a4
; RV32ZBB-NEXT: srli a5, a1, 2
; RV32ZBB-NEXT: and a1, a1, a4
; RV32ZBB-NEXT: and a2, a2, a4
; RV32ZBB-NEXT: slli a0, a0, 2
; RV32ZBB-NEXT: and a4, a5, a4
; RV32ZBB-NEXT: slli a1, a1, 2
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a4, a1
; RV32ZBB-NEXT: srli a2, a0, 1
; RV32ZBB-NEXT: and a0, a0, a3
; RV32ZBB-NEXT: srli a4, a1, 1
; RV32ZBB-NEXT: and a1, a1, a3
; RV32ZBB-NEXT: and a2, a2, a3
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: and a3, a4, a3
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: or a0, a2, a0
; RV32ZBB-NEXT: or a1, a3, a1
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: test_bitreverse_bswap_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32
; RV64ZBB-NEXT: add a2, a2, a4
; RV64ZBB-NEXT: slli a4, a3, 32
; RV64ZBB-NEXT: add a3, a3, a4
; RV64ZBB-NEXT: srli a4, a0, 4
; RV64ZBB-NEXT: and a4, a4, a1
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a4, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
; RV64ZBB-NEXT: and a0, a0, a3
; RV64ZBB-NEXT: and a1, a1, a3
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: test_bitreverse_bswap_i64:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: brev8 a1, a1
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_bswap_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
%tmp = call i64 @llvm.bitreverse.i64(i64 %a)
%tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
ret i64 %tmp2
}
define i32 @pr55484(i32 %0) {
; RV32I-LABEL: pr55484:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 8
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: pr55484:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 40
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: pr55484:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a1, a0, 8
; RV32ZBB-NEXT: slli a0, a0, 8
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: sext.h a0, a0
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: pr55484:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 8
; RV64ZBB-NEXT: slli a0, a0, 8
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: sext.h a0, a0
; RV64ZBB-NEXT: ret
;
; RV32ZBKB-LABEL: pr55484:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: slli a1, a0, 8
; RV32ZBKB-NEXT: slli a0, a0, 24
; RV32ZBKB-NEXT: or a0, a0, a1
; RV32ZBKB-NEXT: srai a0, a0, 16
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: pr55484:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: slli a1, a0, 40
; RV64ZBKB-NEXT: slli a0, a0, 56
; RV64ZBKB-NEXT: or a0, a0, a1
; RV64ZBKB-NEXT: srai a0, a0, 48
; RV64ZBKB-NEXT: ret
%2 = lshr i32 %0, 8
%3 = shl i32 %0, 8
%4 = or i32 %2, %3
%5 = trunc i32 %4 to i16
%6 = sext i16 %5 to i32
ret i32 %6
}
Reference in New Issue View Git Blame Copy Permalink