6d03f51f0c
- _Float16 is now accepted by Clang. - The half IR type is fully handled by the backend. - These values are passed in FP registers and converted to/from float around each operation. - Compiler-rt conversion functions are now built for s390x including the missing extendhfdf2 which was added. Fixes #50374
65 lines
2.4 KiB
LLVM
65 lines
2.4 KiB
LLVM
; Test strict conversions of unsigned i32s to floating-point values (z10 only).
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare half @llvm.experimental.constrained.uitofp.f16.i32(i32, metadata, metadata)
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declare float @llvm.experimental.constrained.uitofp.f32.i32(i32, metadata, metadata)
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declare double @llvm.experimental.constrained.uitofp.f64.i32(i32, metadata, metadata)
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declare fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32, metadata, metadata)
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; Check i32->f16. There is no native instruction, so we must promote
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; to i64 first.
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define half @f0(i32 %i) #0 {
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; CHECK-LABEL: f0:
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; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
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; CHECK: cegbr %f0, [[REGISTER]]
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; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
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; CHECK: br %r14
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%conv = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %i,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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ret half %conv
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}
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; Check i32->f32. There is no native instruction, so we must promote
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; to i64 first.
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define float @f1(i32 %i) #0 {
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; CHECK-LABEL: f1:
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; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
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; CHECK: cegbr %f0, [[REGISTER]]
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; CHECK: br %r14
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%conv = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %i,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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ret float %conv
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}
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; Check i32->f64.
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define double @f2(i32 %i) #0 {
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; CHECK-LABEL: f2:
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; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
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; CHECK: cdgbr %f0, [[REGISTER]]
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; CHECK: br %r14
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%conv = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %i,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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ret double %conv
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}
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; Check i32->f128.
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define void @f3(i32 %i, ptr %dst) #0 {
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; CHECK-LABEL: f3:
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; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
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; CHECK: cxgbr %f0, [[REGISTER]]
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; CHECK: std %f0, 0(%r3)
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; CHECK: std %f2, 8(%r3)
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; CHECK: br %r14
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%conv = call fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32 %i,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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store fp128 %conv, ptr %dst
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ret void
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}
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attributes #0 = { strictfp }
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