6d03f51f0c
- _Float16 is now accepted by Clang. - The half IR type is fully handled by the backend. - These values are passed in FP registers and converted to/from float around each operation. - Compiler-rt conversion functions are now built for s390x including the missing extendhfdf2 which was added. Fixes #50374
114 lines
3.0 KiB
LLVM
114 lines
3.0 KiB
LLVM
; Test the Test Data Class instruction logic operation folding.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @llvm.s390.tdc.f16(half, i64)
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declare i32 @llvm.s390.tdc.f32(float, i64)
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declare i32 @llvm.s390.tdc.f64(double, i64)
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declare i32 @llvm.s390.tdc.f128(fp128, i64)
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; Check using or i1
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define i32 @f0(half %x) {
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; CHECK-LABEL: f0
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; CHECK: brasl %r14, __extendhfsf2@PLT
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; CHECK: tceb %f0, 7
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; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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%a = call i32 @llvm.s390.tdc.f16(half %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f16(half %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = or i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Check using or i1
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define i32 @f1(float %x) {
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; CHECK-LABEL: f1
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; CHECK: tceb %f0, 7
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; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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%a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = or i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Check using and i1
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define i32 @f2(double %x) {
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; CHECK-LABEL: f2
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; CHECK: tcdb %f0, 2
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; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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%a = call i32 @llvm.s390.tdc.f64(double %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f64(double %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = and i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Check using xor i1
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define i32 @f3(fp128 %x) {
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; CHECK-LABEL: f3
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; CHECK: tcxb %f0, 5
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; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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%a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = xor i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Check using xor i1 - negated test
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define i32 @f4(fp128 %x) {
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; CHECK-LABEL: f4
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; CHECK: tcxb %f0, 4090
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; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
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; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
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%a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp eq i32 %b, 0
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%res = xor i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Check different first args
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define i32 @f5(float %x, float %y) {
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; CHECK-LABEL: f5
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; CHECK-NOT: tceb {{%f[0-9]+}}, 5
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; CHECK-DAG: tceb %f0, 3
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; CHECK-DAG: tceb %f2, 6
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%a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
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%b = call i32 @llvm.s390.tdc.f32(float %y, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = xor i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Non-const mask (not supported)
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define i32 @f6(float %x, i64 %y) {
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; CHECK-LABEL: f6
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; CHECK-DAG: tceb %f0, 0(%r2)
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; CHECK-DAG: tceb %f0, 6
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%a = call i32 @llvm.s390.tdc.f32(float %x, i64 %y)
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%b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
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%a1 = icmp ne i32 %a, 0
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%b1 = icmp ne i32 %b, 0
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%res = xor i1 %a1, %b1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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