80267f8148
The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
73 lines
2.4 KiB
LLVM
73 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test widening vector multiply-and-add on z17.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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; Test a v2i64 (even) -> i128 unsigned widening multiply-and-add.
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define i128 @f1(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaleg %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%elt1 = extractelement <2 x i64> %val1, i32 0
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%zext1 = zext i64 %elt1 to i128
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%elt2 = extractelement <2 x i64> %val2, i32 0
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%zext2 = zext i64 %elt2 to i128
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%mul = mul i128 %zext1, %zext2
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%ret = add i128 %mul, %val3
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ret i128 %ret
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}
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; Test a v2i64 (odd) -> i128 unsigned widening multiply-and-add.
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define i128 @f2(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmalog %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%elt1 = extractelement <2 x i64> %val1, i32 1
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%zext1 = zext i64 %elt1 to i128
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%elt2 = extractelement <2 x i64> %val2, i32 1
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%zext2 = zext i64 %elt2 to i128
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%mul = mul i128 %zext1, %zext2
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%ret = add i128 %mul, %val3
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ret i128 %ret
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}
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; Test a v2i64 (even) -> i128 signed widening multiply-and-add.
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define i128 @f3(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaeg %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%elt1 = extractelement <2 x i64> %val1, i32 0
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%sext1 = sext i64 %elt1 to i128
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%elt2 = extractelement <2 x i64> %val2, i32 0
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%sext2 = sext i64 %elt2 to i128
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%mul = mul i128 %sext1, %sext2
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%ret = add i128 %mul, %val3
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ret i128 %ret
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}
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; Test a v2i64 (odd) -> i128 signed widening multiply-and-add.
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define i128 @f4(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaog %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%elt1 = extractelement <2 x i64> %val1, i32 1
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%sext1 = sext i64 %elt1 to i128
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%elt2 = extractelement <2 x i64> %val2, i32 1
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%sext2 = sext i64 %elt2 to i128
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%mul = mul i128 %sext1, %sext2
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%ret = add i128 %mul, %val3
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ret i128 %ret
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}
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