ee13638362
Since e39f6c1844 opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.
Reviewed By: shiltian, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/137921
68 lines
2.4 KiB
LLVM
68 lines
2.4 KiB
LLVM
; RUN: opt -mtriple=amdgcn--amdhsa -S -passes=inline -inline-threshold=0 < %s | FileCheck %s
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define void @use_flat_ptr_arg(ptr nocapture %p) {
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entry:
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%tmp1 = load float, ptr %p, align 4
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%div = fdiv float 1.000000e+00, %tmp1
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%add0 = fadd float %div, 1.0
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%add1 = fadd float %add0, 1.0
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%add2 = fadd float %add1, 1.0
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%add3 = fadd float %add2, 1.0
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%add4 = fadd float %add3, 1.0
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%add5 = fadd float %add4, 1.0
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%add6 = fadd float %add5, 1.0
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%add7 = fadd float %add6, 1.0
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%add8 = fadd float %add7, 1.0
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%add9 = fadd float %add8, 1.0
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%add10 = fadd float %add9, 1.0
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store float %add10, ptr %p, align 4
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ret void
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}
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define void @use_private_ptr_arg(ptr addrspace(5) nocapture %p) {
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entry:
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%tmp1 = load float, ptr addrspace(5) %p, align 4
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%div = fdiv float 1.000000e+00, %tmp1
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%add0 = fadd float %div, 1.0
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%add1 = fadd float %add0, 1.0
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%add2 = fadd float %add1, 1.0
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%add3 = fadd float %add2, 1.0
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%add4 = fadd float %add3, 1.0
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%add5 = fadd float %add4, 1.0
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%add6 = fadd float %add5, 1.0
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%add7 = fadd float %add6, 1.0
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%add8 = fadd float %add7, 1.0
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%add9 = fadd float %add8, 1.0
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%add10 = fadd float %add9, 1.0
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store float %add10, ptr addrspace(5) %p, align 4
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ret void
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}
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; Test that the inline threshold is boosted if called with an
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; addrspacecasted' alloca.
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; CHECK-LABEL: @test_inliner_flat_ptr(
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; CHECK: call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NOT: call {{[.*]}}@
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define amdgpu_kernel void @test_inliner_flat_ptr(ptr addrspace(1) nocapture %a, i32 %n) {
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entry:
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%pvt_arr = alloca [64 x float], align 4, addrspace(5)
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
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%tmp2 = load float, ptr addrspace(1) %arrayidx, align 4
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%add = add i32 %tid, 1
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%arrayidx2 = getelementptr inbounds float, ptr addrspace(1) %a, i32 %add
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%tmp5 = load float, ptr addrspace(1) %arrayidx2, align 4
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%or = or i32 %tid, %n
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%arrayidx5 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
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%arrayidx7 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
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%to.flat = addrspacecast ptr addrspace(5) %arrayidx7 to ptr
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call void @use_private_ptr_arg(ptr addrspace(5) %arrayidx7)
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call void @use_flat_ptr_arg(ptr %to.flat)
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { noinline }
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attributes #1 = { nounwind readnone }
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