5fbd0658a0
Add an initial CFG simplification transform, which removes the dead edges for blocks terminated with BranchOnCond true. At the moment, this removes the edge between middle block and scalar preheader when folding the tail. PR: https://github.com/llvm/llvm-project/pull/106748
105 lines
5.8 KiB
LLVM
105 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=loop-vectorize -mcpu=neoverse-v1 -force-vector-interleave=2 -force-vector-width=1 -S %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define i32 @pr70988(ptr %src, i32 %n) {
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; CHECK-LABEL: define i32 @pr70988(
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; CHECK-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[N]], 15
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP1]], i32 1)
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; CHECK-NEXT: [[UMAX:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], 1
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = icmp ult i64 0, [[UMAX]]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY1:%.*]] = icmp ult i64 1, [[UMAX]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE5:%.*]] ]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_LOAD_CONTINUE5]] ]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY1]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT7:%.*]], [[PRED_LOAD_CONTINUE5]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[PRED_LOAD_CONTINUE5]] ]
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; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP18:%.*]], [[PRED_LOAD_CONTINUE5]] ]
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; CHECK-NEXT: br i1 [[ACTIVE_LANE_MASK]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
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; CHECK: pred.load.if:
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
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; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]]
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; CHECK: pred.load.continue:
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; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ poison, [[VECTOR_BODY]] ], [ [[TMP6]], [[PRED_LOAD_IF]] ]
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; CHECK-NEXT: br i1 [[ACTIVE_LANE_MASK2]], label [[PRED_LOAD_IF4:%.*]], label [[PRED_LOAD_CONTINUE5]]
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; CHECK: pred.load.if4:
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; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
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; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
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; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE5]]
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; CHECK: pred.load.continue5:
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; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ poison, [[PRED_LOAD_CONTINUE]] ], [ [[TMP12]], [[PRED_LOAD_IF4]] ]
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; CHECK-NEXT: [[TMP15:%.*]] = tail call i32 @llvm.smax.i32(i32 [[TMP8]], i32 [[VEC_PHI]])
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; CHECK-NEXT: [[TMP16:%.*]] = tail call i32 @llvm.smax.i32(i32 [[TMP14]], i32 [[VEC_PHI3]])
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; CHECK-NEXT: [[TMP17]] = select i1 [[ACTIVE_LANE_MASK]], i32 [[TMP15]], i32 [[VEC_PHI]]
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; CHECK-NEXT: [[TMP18]] = select i1 [[ACTIVE_LANE_MASK2]], i32 [[TMP16]], i32 [[VEC_PHI3]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[INDEX_NEXT]], 1
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = icmp ult i64 [[INDEX_NEXT]], [[UMAX]]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT7]] = icmp ult i64 [[TMP19]], [[UMAX]]
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; CHECK-NEXT: [[TMP20:%.*]] = xor i1 [[ACTIVE_LANE_MASK_NEXT]], true
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; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP17]], i32 [[TMP18]])
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDUC:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDUC_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[MAX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[TMP24:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[INDUC]]
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; CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[GEP]], align 8
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; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
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; CHECK-NEXT: [[TMP24]] = tail call i32 @llvm.smax.i32(i32 [[TMP23]], i32 [[MAX]])
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; CHECK-NEXT: [[INDUC_NEXT]] = add nuw nsw i64 [[INDUC]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDUC_NEXT]], [[UMAX]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[TMP24]], [[LOOP]] ], [ [[RDX_MINMAX]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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entry:
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%1 = and i32 %n, 15
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%2 = call i32 @llvm.umax.i32(i32 %1, i32 1)
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%umax = zext i32 %2 to i64
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br label %loop
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loop:
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%induc = phi i64 [ 0, %entry ], [ %induc.next, %loop ]
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%max = phi i32 [ 0, %entry ], [ %5, %loop ]
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%gep = getelementptr i32, ptr %src, i64 %induc
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%3 = load ptr, ptr %gep
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%4 = load i32, ptr %3
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%5 = tail call i32 @llvm.smax.i32(i32 %4, i32 %max)
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%induc.next = add nuw nsw i64 %induc, 1
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%exitcond.not = icmp eq i64 %induc.next, %umax
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i32 [ %5, %loop ]
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ret i32 %res
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}
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declare i32 @llvm.smax.i32(i32, i32)
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declare i32 @llvm.umax.i32(i32, i32)
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
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;.
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