5fbd0658a0
Add an initial CFG simplification transform, which removes the dead edges for blocks terminated with BranchOnCond true. At the moment, this removes the edge between middle block and scalar preheader when folding the tail. PR: https://github.com/llvm/llvm-project/pull/106748
107 lines
5.4 KiB
LLVM
107 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S -passes=loop-vectorize < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; PR 81872 explains the issue.
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; If we vectorize, we have a miscompile where array IV and thereby value stored in (arr[99],
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; arr[98]) is calculated incorrectly since disjoint or was only disjoint because
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; of dominating conditions. Dropping the disjoint to avoid poison still changes
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; the behaviour since now the or is no longer equivalent to the add.
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;
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define void @test(ptr noundef align 8 dereferenceable_or_null(16) %arr) #0 {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr noundef align 8 dereferenceable_or_null(16) [[ARR:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: bb5:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]], !prof [[PROF0:![0-9]+]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 99, i64 98, i64 97, i64 96>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 99, [[INDEX]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[VEC_IV]], splat (i64 8)
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; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i64> [[VEC_IND]], splat (i64 1)
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[TMP2]], zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[ARR]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[TMP6]], i32 0
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP7]], i32 -3
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; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i1> [[TMP4]], <4 x i1> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr [[TMP8]], i32 8, <4 x i1> [[REVERSE]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 -4)
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF1:![0-9]+]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[BB6:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 99, [[BB5:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[IV]], 1
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; CHECK-NEXT: [[ICMP17:%.*]] = icmp eq i64 [[AND]], 0
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; CHECK-NEXT: br i1 [[ICMP17]], label [[BB18:%.*]], label [[LOOP_LATCH]], !prof [[PROF5:![0-9]+]]
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; CHECK: bb18:
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; CHECK-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1
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; CHECK-NEXT: [[GETELEMENTPTR19:%.*]] = getelementptr inbounds i64, ptr [[ARR]], i64 [[OR]]
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; CHECK-NEXT: store i64 1, ptr [[GETELEMENTPTR19]], align 8
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
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; CHECK-NEXT: [[ICMP22:%.*]] = icmp eq i64 [[IV_NEXT]], 90
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; CHECK-NEXT: br i1 [[ICMP22]], label [[BB6]], label [[LOOP_HEADER]], !prof [[PROF6:![0-9]+]], !llvm.loop [[LOOP7:![0-9]+]]
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; CHECK: bb6:
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; CHECK-NEXT: ret void
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;
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bb5:
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br label %loop.header
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loop.header: ; preds = %loop.latch, %bb8
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%iv = phi i64 [ 99, %bb5 ], [ %iv.next, %loop.latch ]
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%and = and i64 %iv, 1
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%icmp17 = icmp eq i64 %and, 0
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br i1 %icmp17, label %bb18, label %loop.latch, !prof !21
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bb18: ; preds = %loop.header
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%or = or disjoint i64 %iv, 1
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%getelementptr19 = getelementptr inbounds i64, ptr %arr, i64 %or
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store i64 1, ptr %getelementptr19, align 8
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br label %loop.latch
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loop.latch: ; preds = %bb18, %loop.header
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%iv.next = add nsw i64 %iv, -1
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%icmp22 = icmp eq i64 %iv.next, 90
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br i1 %icmp22, label %bb6, label %loop.header, !prof !22
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bb6:
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ret void
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}
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attributes #0 = {"target-cpu"="haswell" "target-features"="+avx2" }
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!4 = !{}
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!10 = !{i32 1}
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!16 = !{i64 864}
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!17 = !{i64 8}
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!21 = !{!"branch_weights", i32 1, i32 1}
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!22 = !{!"branch_weights", i32 1, i32 95}
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;.
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; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 127}
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; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 23}
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; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
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; CHECK: [[META3]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META4]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[PROF5]] = !{!"branch_weights", i32 1, i32 1}
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; CHECK: [[PROF6]] = !{!"branch_weights", i32 0, i32 0}
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; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]], [[META3]]}
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;.
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