Files
clang-p2996/llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
Alexey Bataev 2271f0bebd [SLP]Check for perfect/shuffled match for the split node
If the potential split node is a perfect/shuffled match of another split
node, need to skip creation of the another split node with the same
scalars, it should be a buildvector.

Fixes #135800
2025-04-15 13:17:46 -07:00

73 lines
3.9 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-sie-ps5 -mcpu=znver2 < %s | FileCheck %s
define i1 @test(ptr %0, ptr %1, <2 x float> %2, <2 x float> %3, <2 x float> %4) {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], <2 x float> [[TMP3:%.*]], <2 x float> [[TMP4:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP4]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[TMP6]], i32 0
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x float> [[TMP10]], float [[TMP7]], i32 1
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> [[TMP11]], float [[TMP8]], i32 6
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x float> [[TMP12]], <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 6, i32 6>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP3]], <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 poison>
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[TMP9]], i32 7
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <8 x float> [[TMP13]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP18:%.*]] = call <16 x float> @llvm.vector.insert.v16f32.v8f32(<16 x float> [[TMP16]], <8 x float> [[TMP15]], i64 8)
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <8 x float> [[TMP14]], <8 x float> [[TMP12]], <16 x i32> <i32 8, i32 9, i32 9, i32 9, i32 9, i32 9, i32 14, i32 14, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP9]], i32 15
; CHECK-NEXT: [[TMP20:%.*]] = fmul <16 x float> [[TMP18]], [[TMP17]]
; CHECK-NEXT: [[TMP21:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> [[TMP20]])
; CHECK-NEXT: [[TMP22:%.*]] = call float @foo(float [[TMP21]])
; CHECK-NEXT: ret i1 false
;
%6 = load float, ptr %1, align 4
%7 = load float, ptr %0, align 4
%8 = fmul float %6, %6
%9 = fmul float %7, %7
%10 = fmul float %7, %7
%11 = fmul float %7, %7
%12 = fmul float %7, %7
%13 = fmul float %7, %7
%14 = load float, ptr %0, align 4
%15 = fmul float %14, %14
%16 = fmul float %14, %14
%17 = extractelement <2 x float> %2, i64 0
%18 = extractelement <2 x float> %2, i64 0
%19 = fmul float %17, %17
%20 = fmul float %18, %18
%21 = extractelement <2 x float> %3, i64 0
%22 = extractelement <2 x float> %2, i64 0
%23 = fmul float %21, %21
%24 = fmul float %22, %22
%25 = extractelement <2 x float> %2, i64 0
%26 = extractelement <2 x float> %2, i64 0
%27 = fmul float %25, %25
%28 = fmul float %26, %26
%29 = extractelement <2 x float> %2, i64 0
%30 = extractelement <2 x float> %4, i64 0
%31 = fmul float %29, %29
%32 = fmul float %30, %30
%33 = fadd reassoc nsz float %8, %9
%34 = fadd reassoc nsz float %33, %10
%35 = fadd reassoc nsz float %34, %11
%36 = fadd reassoc nsz float %35, %12
%37 = fadd reassoc nsz float %36, %13
%38 = fadd reassoc nsz float %37, %15
%39 = fadd reassoc nsz float %38, %16
%40 = fadd reassoc nsz float %39, %19
%41 = fadd reassoc nsz float %40, %20
%42 = fadd reassoc nsz float %41, %23
%43 = fadd reassoc nsz float %42, %24
%44 = fadd reassoc nsz float %43, %27
%45 = fadd reassoc nsz float %44, %28
%46 = fadd reassoc nsz float %45, %31
%47 = fadd reassoc nsz float %46, %32
%48 = call float @foo(float %47)
ret i1 false
}
declare float @foo(float)