d41e517748
We use the term "interchangeable instructions" to refer to different operators that have the same meaning (e.g., `add x, 0` is equivalent to `mul x, 1`). Non-constant values are not supported, as they may incur high costs with little benefit. --------- Co-authored-by: Alexey Bataev <a.bataev@gmx.com>
38 lines
1.7 KiB
LLVM
38 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=X86 %}
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; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=AARCH64 %}
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define <2 x i32> @test(i32 %arg) {
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; X86-LABEL: define <2 x i32> @test(
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; X86-SAME: i32 [[ARG:%.*]]) {
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; X86-NEXT: bb:
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; X86-NEXT: [[OR:%.*]] = or i32 [[ARG]], 0
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; X86-NEXT: [[MUL:%.*]] = mul i32 0, 1
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; X86-NEXT: [[MUL1:%.*]] = mul i32 [[OR]], [[MUL]]
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; X86-NEXT: [[CMP:%.*]] = icmp ugt i32 0, [[MUL1]]
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; X86-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[OR]], i32 0
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; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[MUL]], i32 1
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; X86-NEXT: ret <2 x i32> [[TMP1]]
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;
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; AARCH64-LABEL: define <2 x i32> @test(
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; AARCH64-SAME: i32 [[ARG:%.*]]) {
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; AARCH64-NEXT: bb:
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; AARCH64-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 [[ARG]], i32 0
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; AARCH64-NEXT: [[TMP1:%.*]] = mul <2 x i32> [[TMP0]], zeroinitializer
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; AARCH64-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
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; AARCH64-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
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; AARCH64-NEXT: [[MUL1:%.*]] = mul i32 [[TMP2]], [[TMP3]]
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; AARCH64-NEXT: [[CMP:%.*]] = icmp ugt i32 0, [[MUL1]]
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; AARCH64-NEXT: ret <2 x i32> [[TMP1]]
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;
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bb:
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%or = or i32 %arg, 0
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%mul = mul i32 0, 1
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%mul1 = mul i32 %or, %mul
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%cmp = icmp ugt i32 0, %mul1
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%0 = insertelement <2 x i32> poison, i32 %or, i32 0
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%1 = insertelement <2 x i32> %0, i32 %mul, i32 1
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ret <2 x i32> %1
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}
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