cf6a452cc7
getSameOpcode in some cases may consider 2 compares as having same opcode, even though previously they were considered as alternate. It may happen, because getSameOpcode looses info about previous instructions and their states. Need to use isAlternateInstruction function instead for the correct analysis. Reviewers: RKSimon, hiraditya Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/133769
70 lines
3.8 KiB
LLVM
70 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: %if x86-registered-target %{ opt < %s -passes=slp-vectorizer -slp-revec -mtriple=x86_64 -S | FileCheck %s --check-prefixes=CHECK,X86 %}
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; RUN: %if aarch64-registered-target %{ opt < %s -passes=slp-vectorizer -slp-revec -mtriple=aarch64-unknown-linux-gnu -S | FileCheck %s --check-prefixes=CHECK,AARCH64 %}
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define i1 @logical_and_icmp_diff_preds(<4 x i32> %x) {
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; CHECK-LABEL: @logical_and_icmp_diff_preds(
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, <4 x i32> <i32 1, i32 3, i32 6, i32 0>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <4 x i32> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP6]])
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; CHECK-NEXT: ret i1 [[TMP7]]
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;
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%x0 = extractelement <4 x i32> %x, i32 0
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%x1 = extractelement <4 x i32> %x, i32 1
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%x2 = extractelement <4 x i32> %x, i32 2
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%x3 = extractelement <4 x i32> %x, i32 3
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%c0 = icmp ult i32 %x0, 0
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%c1 = icmp slt i32 %x1, 0
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%c2 = icmp sgt i32 %x2, 0
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%c3 = icmp slt i32 %x3, 0
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%s1 = select i1 %c0, i1 %c1, i1 false
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%s2 = select i1 %s1, i1 %c2, i1 false
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%s3 = select i1 %s2, i1 %c3, i1 false
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ret i1 %s3
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}
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define i1 @logical_and_icmp_clamp(<4 x i32> %x) {
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; X86-LABEL: @logical_and_icmp_clamp(
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; X86-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[X:%.*]], splat (i32 42)
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; X86-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 17)
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; X86-NEXT: [[TMP3:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
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; X86-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.vector.insert.v8i1.v4i1(<8 x i1> [[TMP3]], <4 x i1> [[TMP1]], i64 4)
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; X86-NEXT: [[TMP5:%.*]] = freeze <8 x i1> [[TMP4]]
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; X86-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> [[TMP5]])
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; X86-NEXT: ret i1 [[TMP6]]
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;
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; AARCH64-LABEL: @logical_and_icmp_clamp(
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; AARCH64-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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; AARCH64-NEXT: [[TMP2:%.*]] = icmp sgt <8 x i32> [[TMP1]], <i32 17, i32 17, i32 17, i32 17, i32 42, i32 42, i32 42, i32 42>
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; AARCH64-NEXT: [[TMP3:%.*]] = icmp slt <8 x i32> [[TMP1]], <i32 17, i32 17, i32 17, i32 17, i32 42, i32 42, i32 42, i32 42>
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; AARCH64-NEXT: [[TMP4:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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; AARCH64-NEXT: [[TMP5:%.*]] = freeze <8 x i1> [[TMP4]]
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; AARCH64-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> [[TMP5]])
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; AARCH64-NEXT: ret i1 [[TMP6]]
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;
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%x0 = extractelement <4 x i32> %x, i32 0
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%x1 = extractelement <4 x i32> %x, i32 1
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%x2 = extractelement <4 x i32> %x, i32 2
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%x3 = extractelement <4 x i32> %x, i32 3
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%c0 = icmp slt i32 %x0, 42
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%c1 = icmp slt i32 %x1, 42
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%c2 = icmp slt i32 %x2, 42
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%c3 = icmp slt i32 %x3, 42
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%d0 = icmp sgt i32 %x0, 17
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%d1 = icmp sgt i32 %x1, 17
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%d2 = icmp sgt i32 %x2, 17
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%d3 = icmp sgt i32 %x3, 17
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%s1 = select i1 %c0, i1 %c1, i1 false
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%s2 = select i1 %s1, i1 %c2, i1 false
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%s3 = select i1 %s2, i1 %c3, i1 false
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%s4 = select i1 %s3, i1 %d0, i1 false
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%s5 = select i1 %s4, i1 %d1, i1 false
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%s6 = select i1 %s5, i1 %d2, i1 false
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%s7 = select i1 %s6, i1 %d3, i1 false
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ret i1 %s7
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}
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